This patch series refactor existing support for Identify Switch Device and Get Physical Port State by utilizing physical ports (USP & DSP) information stored during enumeration. Additionally, it introduces new support for Physical Port Control of FM-API based physical switch command set as per CXL spec r3.2 Table 8-230:Physical Switch.
This v2 patch series addresses feedback from v1 and incorporates some new changes. It merges [PATCH 1/3] and [PATCH 2/3] from the v1 series, resulting in total of two patches in this patch series. Change log [PATCH v2 1/2]: -namespace defines intead of enum for current_port_config_state. -Relocates all defines & enums to include/hw/cxl/cxl_device.h for improved readibility. -Total number of unique physical ports defined as 256 since the length of number of physical ports given in CXL r3.2 Table 7-16 is 1 byte. Thus, dropping any dependencies on virtual heirarchy throughout the implementation as the request is per switch. -Moves struct phy_port to CXLUpstreamPort avoiding cci specific handling of physical ports hence making it more reasonable. -Utilizes pci_for_each_device_under_bus() to store downstream ports info. -Declarations at the beginning of the function. Change log [PATCH v2 2/2]: -cxl_find_port_dev() now locates device objects for both USP and DSP as physical port control request includes all physical ports. -Replaces qemu_mutex_lock with QEMU_LOCK_GUARD. -Holding reset phase for 100ms added as backgroung operation using qemu_thread_create(). -Updates naming function/variables names as suggested by using lower_case style wherever apt. -Removes CCI sepcific implementation for Assert-Deassert PERST & Reset as it is port wise and utilize struct phy_port stored in CXLUpstreamPort as per [PATCH 1/2]. -Changes made does not lock up other emulations. Logic behind physical port control request: -Assert-Deassert PERST: Assert PERST involves physical port to be in hold reset phase for minimum 100ms. No other physical port control request are entertained until Deassert PERST command for the given port is issued. -Reset PPB: cold reset of physical port (completing enter->hold->exit phases). The Physcial port control request is tested through libcxl-mi interface. It tests all active ports and all opcodes per active port. Since it does not support run time input, all other possible edge cases were tested manually: https://github.com/computexpresslink/libcxlmi/pull/31 Qemu Topology used and it's results: -without any devices connected to downstream ports - success -with virtio-rng-pci devices connected to downstream ports - success -with CXLType3 devices connected to downstream ports - failure -with different unique values of ports (both upstream and downstream) - success Below given topology is an example topology with 3 downstream ports and 1 upstream port. It has one virtio-rng-pci device connected to downstream port 4. FM="-object memory-backend-file,id=cxl-mem1,mem-path=$TMP_DIR/t3_cxl1.raw,size=256M \ -object memory-backend-file,id=cxl-lsa1,mem-path=$TMP_DIR/t3_lsa1.raw,size=1M \ -object memory-backend-file,id=cxl-mem2,mem-path=$TMP_DIR/t3_cxl2.raw,size=16M \ -object memory-backend-file,id=cxl-lsa2,mem-path=$TMP_DIR/t3_lsa2.raw,size=1M \ -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1,hdm_for_passthrough=true \ -device cxl-rp,port=0,bus=cxl.1,id=cxl_rp_port0,chassis=0,slot=2 \ -device cxl-upstream,port=2,sn=1234,bus=cxl_rp_port0,id=us0,addr=0.0,multifunction=on, \ -device cxl-switch-mailbox-cci,bus=cxl_rp_port0,addr=0.1,target=us0 \ -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ -device cxl-downstream,port=4,bus=us0,id=swport1,chassis=0,slot=5 \ -device cxl-downstream,port=8,bus=us0,id=swport2,chassis=0,slot=6 \ -machine cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=1k \ -device i2c_mctp_cxl,bus=aspeed.i2c.bus.0,address=4,target=us0 \ -device i2c_mctp_cxl,bus=aspeed.i2c.bus.0,address=5,target=us0 \ -device i2c_mctp_cxl,bus=aspeed.i2c.bus.0,address=6,target=us0 \ -device virtio-rng-pci,bus=swport1" Observation/Finding: The assert-deassert and reset PPB operation fails when downstream ports are connected to a CXLType3 device as it would mean device reset instead of switch port reset. The patches are generated against the Johnathan's tree https://gitlab.com/jic23/qemu.git and branch cxl-2025-03-20. Signed-off-by: Arpit Kumar <arpit1.ku...@samsung.com> Arpit Kumar (2): hw/cxl: Refactored Identify Switch Device & Get Physical Port State hw/cxl: Add Physical Port Control (Opcode 5102h) hw/cxl/cxl-mailbox-utils.c | 364 +++++++++++++++------- include/hw/cxl/cxl_device.h | 92 ++++++ include/hw/pci-bridge/cxl_upstream_port.h | 4 + 3 files changed, 352 insertions(+), 108 deletions(-) -- 2.34.1
