-added assert-deassert PERST implementation
for physical ports (both USP and DSP's).
-assert PERST involves bg operation for holding 100ms.
-reset PPB implementation for physical ports.
Signed-off-by: Arpit Kumar <arpit1.ku...@samsung.com>
---
hw/cxl/cxl-mailbox-utils.c | 135 ++++++++++++++++++++++++++++++++++++
include/hw/cxl/cxl_device.h | 10 +++
2 files changed, 145 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index c4e83fb2aa..3aa8bd14b9 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -118,6 +118,7 @@ enum {
PHYSICAL_SWITCH = 0x51,
#define IDENTIFY_SWITCH_DEVICE 0x0
#define GET_PHYSICAL_PORT_STATE 0x1
+ #define PHYSICAL_PORT_CONTROL 0X2
TUNNEL = 0x53,
#define MANAGEMENT_COMMAND 0x0
MHD = 0x55,
@@ -605,6 +606,121 @@ static CXLRetCode cmd_get_physical_port_state(const
struct cxl_cmd *cmd,
return CXL_MBOX_SUCCESS;
}
+static void *bg_assertcb(void *opaque)
+{
+ struct pperst *perst = opaque;
+
+ /* holding reset phase for 100ms */
+ while (perst->asrt_time--) {
+ usleep(1000);
+ }
+ perst->issued_assert_perst = true;
+ return NULL;
+}
+
+static CXLRetCode deassert_perst(Object *obj, uint8_t pn, CXLUpstreamPort *pp)
+{
+ if (!pp->pports.perst[pn].issued_assert_perst) {
+ return CXL_MBOX_INTERNAL_ERROR;
+ }
+
+ QEMU_LOCK_GUARD(&pp->pports.perst[pn].lock);
+ resettable_release_reset(obj, RESET_TYPE_COLD);
+ pp->pports.perst[pn].issued_assert_perst = false;
+ pp->pports.pport_info[pn].link_state_flags &=
+ ~LINK_STATE_FLAG_PERST_ASSERTED;
+ pp->pports.perst[pn].asrt_time = ASSERT_WAIT_TIME_MS;
+
+ return CXL_MBOX_SUCCESS;
+}
+
+static CXLRetCode assert_perst(Object *obj, uint8_t pn, CXLUpstreamPort *pp)
+{
+ if (pp->pports.perst[pn].issued_assert_perst ||
+ pp->pports.perst[pn].asrt_time < ASSERT_WAIT_TIME_MS) {
+ return CXL_MBOX_INTERNAL_ERROR;
+ }
+
+ QEMU_LOCK_GUARD(&pp->pports.perst[pn].lock);
+ pp->pports.pport_info[pn].link_state_flags |=
+ LINK_STATE_FLAG_PERST_ASSERTED;
+ resettable_assert_reset(obj, RESET_TYPE_COLD);
+ qemu_thread_create(&pp->pports.perst[pn].asrt_thread, "assert_thread",
+ bg_assertcb, &pp->pports.perst[pn], QEMU_THREAD_DETACHED);
+
+ return CXL_MBOX_SUCCESS;
+}
+
+static struct PCIDevice *cxl_find_port_dev(uint8_t pn, CXLCCI *cci)
+{
+ CXLUpstreamPort *pp = CXL_USP(cci->d);
+ PCIBus *bus = &PCI_BRIDGE(cci->d)->sec_bus;
+
+ if (pp->pports.pport_info[pn].current_port_config_state ==
+ CXL_PORT_CONFIG_STATE_USP) {
+ PCIDevice *usp_dev = pci_bridge_get_device(bus);
+ return usp_dev;
+ }
+
+ if (pp->pports.pport_info[pn].current_port_config_state ==
+ CXL_PORT_CONFIG_STATE_DSP) {
+ PCIDevice *dsp_dev = pcie_find_port_by_pn(bus, pn);
+ return dsp_dev;
+ }
+ return NULL;
+}
+
+/* CXL r3.2 Section 7.6.7.1.3: Get Physical Port Control (Opcode 5102h) */
+static CXLRetCode cmd_physical_port_control(const struct cxl_cmd *cmd,
+ uint8_t *payload_in,
+ size_t len_in,
+ uint8_t *payload_out,
+ size_t *len_out,
+ CXLCCI *cci)
+{
+ CXLUpstreamPort *pp = CXL_USP(cci->d);
+ PCIDevice *dev;
+ uint8_t ret = CXL_MBOX_SUCCESS;
+
+ struct cxl_fmapi_get_physical_port_control_req_pl {
+ uint8_t ppb_id;
+ uint8_t ports_op;
+ } QEMU_PACKED *in = (void *)payload_in;
+
+ if (len_in < sizeof(*in)) {
+ return CXL_MBOX_INVALID_PAYLOAD_LENGTH;
+ }
+
+ uint8_t pn = in->ppb_id;
+ if (pp->pports.pport_info[pn].port_id != pn) {
+ return CXL_MBOX_INTERNAL_ERROR;
+ }
+
+ dev = cxl_find_port_dev(pn, cci);
+ if (!dev) {
+ return CXL_MBOX_INTERNAL_ERROR;
+ }
+
+ switch (in->ports_op) {
+ case 0:
+ ret = assert_perst(OBJECT(&dev->qdev), pn, pp);
+ break;
+ case 1:
+ ret = deassert_perst(OBJECT(&dev->qdev), pn, pp);
+ break;
+ case 2:
+ if (pp->pports.perst[pn].issued_assert_perst ||
+ pp->pports.perst[pn].asrt_time < ASSERT_WAIT_TIME_MS) {
+ return CXL_MBOX_INTERNAL_ERROR;
+ }
+ device_cold_reset(&dev->qdev);
+ break;
+ default:
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ return ret;
+}
+
/* CXL r3.1 Section 8.2.9.1.2: Background Operation Status (Opcode 0002h) */
static CXLRetCode cmd_infostat_bg_op_sts(const struct cxl_cmd *cmd,
uint8_t *payload_in,
@@ -3579,7 +3695,11 @@ void cxl_init_cci(CXLCCI *cci, size_t payload_max)
void cxl_destroy_cci(CXLCCI *cci)
{
+ CXLUpstreamPort *pp = CXL_USP(cci->d);
qemu_mutex_destroy(&cci->bg.lock);
+ for (int i = 0; i < CXL_MAX_PHY_PORTS; i++) {
+ qemu_mutex_destroy(&pp->pports.perst[i].lock);
+ }
cci->initialized = false;
}
@@ -3798,6 +3918,8 @@ static const struct cxl_cmd
cxl_cmd_set_usp_mctp[256][256] = {
cmd_identify_switch_device, 0, 0 },
[PHYSICAL_SWITCH][GET_PHYSICAL_PORT_STATE] = {
"SWITCH_PHYSICAL_PORT_STATS",
cmd_get_physical_port_state, ~0, 0 },
+ [PHYSICAL_SWITCH][PHYSICAL_PORT_CONTROL] = {
"SWITCH_PHYSICAL_PORT_CONTROL",
+ cmd_physical_port_control, 2, 0 },
[TUNNEL][MANAGEMENT_COMMAND] = { "TUNNEL_MANAGEMENT_COMMAND",
cmd_tunnel_management_cmd, ~0, 0 },
};
@@ -3810,4 +3932,17 @@ void cxl_initialize_usp_mctpcci(CXLCCI *cci, DeviceState
*d, DeviceState *intf,
cci->intf = intf;
cxl_init_cci(cci, payload_max);
cxl_set_phy_port_info(cci);
+ /* physical port control */
+ CXLUpstreamPort *pp = CXL_USP(cci->d);
+ for (int i = 0; i < CXL_MAX_PHY_PORTS; i++) {
+ qemu_mutex_init(&pp->pports.perst[i].lock);
+ pp->pports.perst[i].issued_assert_perst = false;
+ /*
+ * Assert PERST involves physical port to be in
+ * hold reset phase for minimum 100ms. No other
+ * physcial port control requests are entertained
+ * until Deassert PERST command.
+ */
+ pp->pports.perst[i].asrt_time = ASSERT_WAIT_TIME_MS;
+ }
}
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 1fa6cf7536..bb47e671eb 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -128,6 +128,7 @@
(1 << 16))
#define CXL_MAX_PHY_PORTS 256
+#define ASSERT_WAIT_TIME_MS 100 /* Assert - Deassert PERST */
#define LINK_STATE_FLAG_LANE_REVERSED BIT(0)
#define LINK_STATE_FLAG_PERST_ASSERTED BIT(1)
@@ -203,10 +204,19 @@ struct cxl_phy_port_info {
uint8_t supported_ld_count;
} QEMU_PACKED;
+/* Assert - Deassert PERST */
+struct pperst {
+ bool issued_assert_perst;
+ QemuMutex lock;
+ uint64_t asrt_time;
+ QemuThread asrt_thread; /* thread for 100ms delay */
+};
+
struct phy_port {
uint8_t num_ports;
uint8_t active_port_bitmask[0x20];
struct cxl_phy_port_info pport_info[CXL_MAX_PHY_PORTS];
+ struct pperst perst[CXL_MAX_PHY_PORTS];
};
/* CXL r3.1 Table 8-34: Command Return Codes */
--
2.34.1
