The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c8cf0ab417..0f64c7b163 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1717,6 +1717,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) /* Return the current FPSCR value. */ -- 2.34.1
