This series adds support for all FEAT_MEC registers to the arm64 max CPU. It includes the FEAT_MEC registers but does not modify the translation regimes to support the MECIDs. It also does not implement the two cache management yet.
I'm currently exploring possibilities to support FEAT_MEC encryption (or obfuscation, for testing purposes) in QEMU for the various translation regimes used on arm64. Cheers, Gustavo Gustavo Romero (5): target/arm: Add the MECEn SCR_EL3 bit target/arm: Add FEAT_MEC registers target/arm: Add FEAT_SCTLR2 target/arm: Add FEAT_TCR2 target/arm: Advertise FEAT_MEC in cpu max docs/system/arm/emulation.rst | 3 + target/arm/cpu-features.h | 15 +++ target/arm/cpu.h | 29 +++++ target/arm/helper.c | 208 ++++++++++++++++++++++++++++++++++ target/arm/internals.h | 20 ++++ target/arm/tcg/cpu64.c | 3 + 6 files changed, 278 insertions(+) -- 2.34.1
