Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks <ben.do...@codethink.co.uk>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..3daf75568c 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -34,6 +34,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
+#define TYPE_RISCV_CPU_CVA6 RISCV_CPU_TYPE_NAME("cva6")
#define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i")
#define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e")
#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 629ac37501..fca45dc9d9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3009,6 +3009,17 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64,
),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_CVA6, TYPE_RISCV_VENDOR_CPU,
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVS | RVU,
+ .misa_mxl_max = MXL_RV64,
+ .cfg.max_satp_mode = VM_1_10_SV39,
+ .priv_spec = PRIV_VERSION_1_12_0,
+ .cfg.pmp = true,
+ .cfg.mmu = true,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ ),
+
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
.misa_mxl_max = MXL_RV64
),
--
2.37.2.352.g3c44437643
