On 09/06/2025 12:30, Daniel Henrique Barboza wrote:
On 6/9/25 7:40 AM, Ben Dooks wrote:
On 07/06/2025 21:17, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks <ben.do...@codethink.co.uk>
---
The README states right at the start:
"CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-
bit RISC-V instruction set."
So this means that CVA6 is a 64-bit CPU only. This means that we want
the second
option: the CPU declaration is fine, but the CVA6 board must be built
only for 64
bits. In patch 1, this line:
config CVA6
bool
default y
depends on RISCV32 || RISCV64 <------------------
Should be "depends on RISCV64".
I think given the confusion, let's go with the RISCV64 for now and if
it turns out there is an 32-bit build option we can always add it in
later and change anything else around.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
