On Wed, 20 Jan 2021 04:05:02 +0100 Marek Vasut wrote:
> KSZ8794CNX datasheet section 8.0 RESET CIRCUIT describes recommended
> circuit for interfacing with CPU/FPGA reset consisting of 10k pullup
> resistor and 10uF capacitor to ground. This circuit takes ~100 ms to
> rise enough to release the reset.
>
> For maximum supply voltage VDDIO=3.3V VIH=2.0V R=10kR C=10uF that is
> VDDIO - VIH
> t = R * C * -ln( ------------- ) = 10000*0.00001*-(-0.93)=0.093 s
> VDDIO
> so we need ~95 ms for the reset to really de-assert, and then the
> original 100us for the switch itself to come out of reset. Simply
> msleep() for 100 ms which fits the constraint with a bit of extra
> space.
>
> Fixes: 5b797980908a ("net: dsa: microchip: Implement recommended reset
> timing")
> Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
> Signed-off-by: Marek Vasut <ma...@denx.de>
I'm slightly confused whether this is just future proofing or you
actually have a board where this matters. The tree is tagged as
net-next but there is a Fixes tag which normally indicates net+stable.
Please advise.
