On Tue, 12 Jan 2021 20:54:04 +0100 Marek Behún <ka...@kernel.org> wrote:
> + /* mv88e6393x family errata 3.7 : > + * When changing cmode on SERDES port from any other mode to 1000BASE-X > + * mode the link may not come up due to invalid 1000BASE-X > + * advertisement. > + * Workaround: Correct advertisement and reset PHY core. > + */ > + if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX) { > + reg = MV88E6390_SGMII_ANAR_1000BASEX_FD; > + err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, > + MV88E6390_SGMII_ANAR, reg); > + if (err) > + return err; > + > + /* soft reset the PCS/PMA */ > + err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, > + MV88E6390_SGMII_CONTROL, ®); > + if (err) > + return err; > + > + reg |= MV88E6390_SGMII_CONTROL_RESET; > + err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, > + MV88E6390_SGMII_CONTROL, reg); > + if (err) > + return err; It would seem that this is already done in mv88e6390_serdes_pcs_config, just without the last reset. > +#define MV88E6390_SGMII_STATUS_AN_ABLE BIT(3) > +#define MV88E6390_SGMII_ANAR 0x2004 > +#define MV88E6390_SGMII_ANAR_1000BASEX_FD BIT(5) > +#define MV88E6390_SGMII_CONTROL 0x2000 This register is already called MV88E6390_SGMII_BMCR and the bits are defined as BMCR_* macros. Thse same for MV88E6390_SGMII_STATUS and MV88E6390_SGMII_ANAR. > +#define MV88E6390_SGMII_CONTROL_RESET BIT(15) > +#define MV88E6390_SGMII_CONTROL_LOOPBACK BIT(14) > +#define MV88E6390_SGMII_CONTROL_PDOWN BIT(11) > +#define MV88E6390_SGMII_STATUS 0x2001 I shall fix this in another version.