On Sat, Jul 11, 2020 at 06:23:49PM +0200, Andrew Lunn wrote:
> So i'm guessing it is the connection between the CPU and the switch.
> Could you confirm this? Create a bridge, add two ports of the switch
> to the bridge, and then see if packets can pass between switch ports.
> 
> If it is the connection between the CPU and the switch, i would then
> be thinking about the comphy and the firmware. We have seen issues
> where the firmware is too old. That is not something i've debugged
> myself, so i don't know where the version information is, or what
> version is required.

However, in the report, Martin said that reverting the problem commit
from April 14th on a kernel from July 6th caused everything to work
again.  That is quite conclusive that 34b5e6a33c1a is the cause of
the breakage.

The question is how - I don't get it.  None of the GT8k DSA ports are
fixed-links, not even the CPU port (which no longer even uses phylink.)
However, the MVPP2 is using a fixed-link on the port that faces the
DSA switch, which doesn't sound like a good idea to me to have
dis-similar configurations at either end.  So the addition of
"|| mode == MLO_AN_FIXED" shouldn't make any difference.

I think some debug printks would be needed to work out what's going on.

-- 
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