On Fri, Jun 19, 2020 at 12:03:31AM +0200, Andrew Lunn wrote:
> > Are there really instances where the ethernet driver has to manage multiple
> > different types of PCSs? I am not sure this type of snippet of code is
> > really
> > going to occur.
>
> Hi Ioana
>
> The Marvell mv88e6390 family has three PCS's, one for SGMII/1000BaseX,
> a 10Gbase-X4/X2 and a 10GBAse-R. So this sort of code could appear.
It in fact already does, but only for the 1G and 10GBase-R cases.
We don't have a PHY interface mode for 10Gbase-X4/X2, so I never
added that, but if it happens, we end up with a third case.
It may be tempting to suggest that moving the mv88e6390 PCS support
to common code would be a good idea, but it's really not - the PCS
don't follow IEEE 802.3 register layout. The 1G registers are in
the PHYXS MMD, following Clause 22 layout at offset 0x2000. The
10GBASE-R registers are in the PHYXS MMD at offset 0x1000.
So, I don't think it's sensible to compare the mv88e6390 switch
with this; the mv88e6390 serdes PCS is unlikely to be useful
outside of the DSA switch environment.
However, the Lynx PCS appears to be used in a range of different
situations, which include DSA switches and conventional ethernet
drivers. That means we need some kind of solution where the code
driving the PCS does not rely on the code structures for the
device it is embedded with.
The solution I've suggested for DSA may help us get towards having
generic PCS drivers, but it doesn't fully solve the problem. I
would ideally like DSA drivers to have access to "struct phylink"
so that they can attach the PCS themselves without having any of
the DSA layering veneers get in the way between phylink and the
PCS code - thereby allowing the PCS code to be re-used cleanly
with a conventional network driver.
Basically, I'm thinking is:
int phylink_attach_pcs(struct phylink *pl, const struct phylink_pcs_ops *ops,
void *pcs_priv);
which the PCS driver itself would call when requested to by the
DSA driver or ethernet driver.
Thoughts?
--
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