From: Dinh Nguyen <dingu...@kernel.org> Date: Wed, 5 Jun 2019 10:05:51 -0500
> On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from > the Cyclone5 and Arria5: > - The emac PHY setup bits are in separate registers. > - The PTP reference clock select mask is different. > - The register to enable the emac signal from FPGA is different. > > Thus, this patch creates a separate function for setting the phy modes on > Arria10/Agilex/Stratix10. The separation is based a new DTS binding: > "altr,socfpga-stmmac-a10-s10". > > Signed-off-by: Dinh Nguyen <dingu...@kernel.org> Applied to net-next.
