[PATCH net-next 4/8] MIPS: dts: mscc: describe the PTP ready interrupt

[Antoine Tenart]

This patch adds a description of the PTP ready interrupt, which can be
triggered when a PTP timestamp is available on an hardware FIFO.

Signed-off-by: Antoine Tenart <antoine.ten...@bootlin.com>
---
 arch/mips/boot/dts/mscc/ocelot.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi 
b/arch/mips/boot/dts/mscc/ocelot.dtsi
index bb81652bebe8..0bf5fa11c4e7 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -139,8 +139,8 @@
                                    "port1", "port2", "port3", "port4", "port5",
                                    "port6", "port7", "port8", "port9",
                                    "port10", "qsys", "ana";
-                       interrupts = <21 22>;
-                       interrupt-names = "xtr", "inj";
+                       interrupts = <18 21 22>;
+                       interrupt-names = "ptp_rdy", "xtr", "inj";
 
                        ethernet-ports {
                                #address-cells = <1>;
-- 
2.20.1