On Mon, 3 Dec 2018 22:42:04 +0000, Paul Burton wrote:
> Jiong Wang wrote:
> > For micro-mips, srlv inside POOL32A encoding space should use 0x50
> > sub-opcode, NOT 0x90.
> >
> > Some early version ISA doc describes the encoding as 0x90 for both srlv and
> > srav, this looks to me was a typo. I checked Binutils libopcode
> > implementation which is using 0x50 for srlv and 0x90 for srav.
> >
> > v1->v2:
> > - Keep mm_srlv32_op sorted by value.
> >
> > Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
> > Cc: Markos Chandras <[email protected]>
> > Cc: Paul Burton <[email protected]>
> > Cc: [email protected]
> > Acked-by: Jakub Kicinski <[email protected]>
> > Acked-by: Song Liu <[email protected]>
> > Signed-off-by: Jiong Wang <[email protected]>
>
> Applied to mips-fixes.
Newbie process related question - are the arch JIT patches routed via
arch trees or bpf-next? Jiong has more (slightly conflicting) JIT
patches to send - I wonder how they'll get applied and whether to wait
for the mips -> Linus -> net -> bpf merge chain.
