From: Jeff Kirsher
> Sent: 03 March 2017 02:25
> From: Alexander Duyck <alexander.h.du...@intel.com>
>
> On architectures that have a cache line size larger than 64 Bytes we start
> running into issues where the amount of headroom for the frame starts
> shrinking.
>
> The size of skb_shared_info on a system with a 64B L1 cache line size is
> 320. This increases to 384 with a 128B cache line, and 512 with a 256B
> cache line.
Perhaps some of the CACHE_LINE_ALIGNED markers don't actually need
to force alignment with large line sizes?
I realise some things have hard requirements for cache alignment
(eg non-coherent dma), but others are just there to limit the number
of cache lines read and/or dirtied.
David
