This patch is optional in the series. It does make the output much cleaner, but
there is some risk.
Sample output:
0x00007180: 0x231d7000: SURF005: 2D R8G8B8A8_UNORM VALIGN4 HALIGN4
Y-tiled
0x00007184: 0x18000000: SURF005: MOCS: 0x18 Base MIP: 3 (0 mips) Surface
QPitch: 0
0x00007188: 0x001f001f: SURF005: 32x32 [AUX_NONE]
0x0000718c: 0x0000007f: SURF005: 1 slices (depth), pitch: 128
0x00007190: 0x00000000: SURF005: min array element: 0, array extent 1,
MULTISAMPLE_1
0x00007194: 0x00000000: SURF005: x,y offset: 0,0, min LOD: 0
0x00007198: 0x00000000: SURF005: AUX pitch: 0 qpitch: 0
0x0000719c: 0x09770000: SURF005: Clear color: ----
0x00007140: 0x231d7000: SURF006: 2D R8G8B8A8_UNORM VALIGN4 HALIGN4
Y-tiled
0x00007144: 0x18000000: SURF006: MOCS: 0x18 Base MIP: 3 (0 mips) Surface
QPitch: 0
0x00007148: 0x001f001f: SURF006: 32x32 [AUX_NONE]
0x0000714c: 0x0000007f: SURF006: 1 slices (depth), pitch: 128
0x00007150: 0x00000000: SURF006: min array element: 0, array extent 1,
MULTISAMPLE_1
0x00007154: 0x00000000: SURF006: x,y offset: 0,0, min LOD: 0
0x00007158: 0x00000000: SURF006: AUX pitch: 0 qpitch: 0
0x0000715c: 0x09770000: SURF006: Clear color: ----
0x00007100: 0x231d7000: SURF007: 2D R8G8B8A8_UNORM VALIGN4 HALIGN4
Y-tiled
0x00007104: 0x18000000: SURF007: MOCS: 0x18 Base MIP: 3 (0 mips) Surface
QPitch: 0
0x00007108: 0x001f001f: SURF007: 32x32 [AUX_NONE]
0x0000710c: 0x0000007f: SURF007: 1 slices (depth), pitch: 128
0x00007110: 0x00000000: SURF007: min array element: 0, array extent 1,
MULTISAMPLE_1
0x00007114: 0x00000000: SURF007: x,y offset: 0,0, min LOD: 0
0x00007118: 0x00000000: SURF007: AUX pitch: 0 qpitch: 0
0x0000711c: 0x09770000: SURF007: Clear color: ----
Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_state.h | 13 ++++++++-----
src/mesa/drivers/dri/i965/brw_state_batch.c | 20 ++++++++++++--------
src/mesa/drivers/dri/i965/brw_state_dump.c | 12 ++++++++----
src/mesa/drivers/dri/i965/gen8_surface_state.c | 15 ++++++++-------
5 files changed, 37 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index f79729b..0a6edcf 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1415,6 +1415,7 @@ struct brw_context
uint32_t offset;
uint32_t size;
enum aub_state_struct_type type;
+ int index;
} *state_batch_list;
int state_batch_count;
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index cfa67b6..7685178 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -205,11 +205,14 @@ void brw_destroy_caches( struct brw_context *brw );
#define BRW_BATCH_STRUCT(brw, s) \
intel_batchbuffer_data(brw, (s), sizeof(*(s)), RENDER_RING)
-void *brw_state_batch(struct brw_context *brw,
- enum aub_state_struct_type type,
- int size,
- int alignment,
- uint32_t *out_offset);
+void *__brw_state_batch(struct brw_context *brw,
+ enum aub_state_struct_type type,
+ int size,
+ int alignment,
+ int index,
+ uint32_t *out_offset);
+#define brw_state_batch(brw, type, size, alignment, out_offset) \
+ __brw_state_batch(brw, type, size, alignment, 0, out_offset)
/* brw_wm_surface_state.c */
void gen4_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c
b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 45dca69..0377606 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -38,7 +38,8 @@ static void
brw_track_state_batch(struct brw_context *brw,
enum aub_state_struct_type type,
uint32_t offset,
- int size)
+ int size,
+ int index)
{
struct intel_batchbuffer *batch = &brw->batch;
@@ -53,6 +54,7 @@ brw_track_state_batch(struct brw_context *brw,
brw->state_batch_list[brw->state_batch_count].offset = offset;
brw->state_batch_list[brw->state_batch_count].size = size;
brw->state_batch_list[brw->state_batch_count].type = type;
+ brw->state_batch_list[brw->state_batch_count].index = index;
brw->state_batch_count++;
}
@@ -108,18 +110,20 @@ brw_annotate_aub(struct brw_context *brw)
* margin (4096 bytes, even if the object is just a 20-byte surface
* state), and more buffers to walk and count for aperture size checking.
*
- * However, due to the restrictions inposed by the aperture size
+ * However, due to the restrictions imposed by the aperture size
* checking performance hacks, we can't have the batch point at a
* separate indirect state buffer, because once the batch points at
* it, no more relocations can be added to it. So, we sneak these
* buffers in at the top of the batchbuffer.
*/
void *
-brw_state_batch(struct brw_context *brw,
- enum aub_state_struct_type type,
- int size,
- int alignment,
- uint32_t *out_offset)
+__brw_state_batch(struct brw_context *brw,
+ enum aub_state_struct_type type,
+ int size,
+ int alignment,
+ int index,
+ uint32_t *out_offset)
+
{
struct intel_batchbuffer *batch = &brw->batch;
uint32_t offset;
@@ -140,7 +144,7 @@ brw_state_batch(struct brw_context *brw,
batch->state_batch_offset = offset;
if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_AUB)))
- brw_track_state_batch(brw, type, offset, size);
+ brw_track_state_batch(brw, type, offset, size, index);
*out_offset = offset;
return batch->map + (offset>>2);
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 60e6b05..7217141 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -487,12 +487,13 @@ static float q_to_float(uint32_t data, int integer_end,
int integer_start,
return n * pow(2, -(fractional_end - fractional_start + 1));
}
-static void dump_gen8_surface_state(struct brw_context *brw, uint32_t offset)
+static void
+dump_gen8_surface_state(struct brw_context *brw, uint32_t offset, int index)
{
- const char *name = "SURF";
uint32_t *surf = brw->batch.bo->virtual + offset;
int aux_mode = surf[7] & INTEL_MASK(2, 0);
const char *aux_str;
+ char *name;
if (brw->gen >= 9) {
bool msrt = GET_BITS(surf[4], 5, 3) > 0;
@@ -508,7 +509,8 @@ static void dump_gen8_surface_state(struct brw_context
*brw, uint32_t offset)
} else
aux_str = surface_aux_mode[aux_mode];
- batch_out(brw, "SURF'", offset, 0, "%s %s %s VALIGN%d HALIGN%d %s\n",
+ asprintf(&name, "SURF%03d", index);
+ batch_out(brw, name, offset, 0, "%s %s %s VALIGN%d HALIGN%d %s\n",
get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)),
(surf[0] & GEN7_SURFACE_IS_ARRAY) ? "array" : "",
@@ -557,6 +559,7 @@ static void dump_gen8_surface_state(struct brw_context
*brw, uint32_t offset)
GET_BITS(surf[7], 28, 28) ? 'A' : '-'
);
}
+ free(name);
}
static void
@@ -942,7 +945,8 @@ dump_state_batch(struct brw_context *brw)
break;
case AUB_TRACE_SURFACE_STATE:
if (brw->gen >= 8) {
- dump_gen8_surface_state(brw, offset);
+ dump_gen8_surface_state(brw, offset,
+ brw->state_batch_list[i].index);
} else if (brw->gen >= 7) {
dump_gen7_surface_state(brw, offset);
} else {
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 011c685..9753bdc 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -100,11 +100,11 @@ horizontal_alignment(struct intel_mipmap_tree *mt)
}
static uint32_t *
-allocate_surface_state(struct brw_context *brw, uint32_t *out_offset)
+allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int
index)
{
int dwords = brw->gen >= 9 ? 16 : 13;
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- dwords * 4, 64, out_offset);
+ uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ dwords * 4, 64, index, out_offset);
memset(surf, 0, dwords * 4);
return surf;
}
@@ -120,7 +120,7 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
bool rw)
{
const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- uint32_t *surf = allocate_surface_state(brw, out_offset);
+ uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
@@ -165,6 +165,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
uint32_t aux_mode = 0;
mesa_format format = intelObj->_Format;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
+ int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
if (tObj->Target == GL_TEXTURE_BUFFER) {
brw_update_buffer_texture_surface(ctx, unit, surf_offset);
@@ -199,7 +200,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
uint32_t tex_format = translate_tex_format(brw, format,
sampler->sRGBDecode);
- uint32_t *surf = allocate_surface_state(brw, surf_offset);
+ uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
tex_format << BRW_SURFACE_FORMAT_SHIFT |
@@ -294,7 +295,7 @@ gen8_emit_null_surface_state(struct brw_context *brw,
unsigned samples,
uint32_t *out_offset)
{
- uint32_t *surf = allocate_surface_state(brw, out_offset);
+ uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
@@ -378,7 +379,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
}
uint32_t *surf =
- allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]);
+ allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index],
surf_index);
surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
(is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
--
2.3.6
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