This is another non-pipelined command that needs a flush on Sandybridge.
Signed-off-by: Kenneth Graunke <[email protected]>
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 5d1c27d..70b0dbd 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -48,6 +48,10 @@ static void upload_drawing_rect(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
+ /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined. */
+ if (brw->gen == 6)
+ intel_emit_post_sync_nonzero_flush(brw);
+
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0); /* xmin, ymin */
--
1.8.3.2
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