From: Marek Olšák <[email protected]>
Compression isn't enabled with non-zero levels.
---
src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 18b070b..b080562 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -425,21 +425,21 @@ void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen,
if (sscreen->b.chip_class >= VI) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
if (vi_dcc_enabled(tex, first_level)) {
meta_va = (!tex->dcc_separate_buffer ?
tex->resource.gpu_address : 0) +
tex->dcc_offset;
if (sscreen->b.chip_class <= VI)
meta_va += base_level_info->dcc_offset;
- } else if (tex->tc_compatible_htile) {
+ } else if (tex->tc_compatible_htile && first_level == 0) {
meta_va = tex->resource.gpu_address + tex->htile_offset;
}
if (meta_va) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
}
}
if (sscreen->b.chip_class >= GFX9) {
--
2.7.4
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