From: Marek Olšák <[email protected]>
---
src/gallium/drivers/r600/evergreen_state.c | 4 +--
src/gallium/drivers/r600/r600_state.c | 4 +--
src/gallium/drivers/radeon/r600_texture.c | 29 ++++++++++++----------
src/gallium/drivers/radeon/radeon_uvd.c | 2 +-
src/gallium/drivers/radeon/radeon_vce.c | 4 +--
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 8 +++---
src/gallium/drivers/radeon/radeon_vce_50.c | 4 +--
src/gallium/drivers/radeon/radeon_vce_52.c | 8 +++---
src/gallium/drivers/radeon/radeon_winsys.h | 1 -
src/gallium/drivers/radeonsi/cik_sdma.c | 4 +--
src/gallium/drivers/radeonsi/si_dma.c | 4 +--
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 1 -
src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 19 ++++++++------
13 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 2167e76..015ff02 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3485,22 +3485,22 @@ static void evergreen_dma_copy(struct pipe_context *ctx,
!r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
dstz, rsrc, src_level, src_box))
goto fallback;
src_x = util_format_get_nblocksx(src->format, src_box->x);
dst_x = util_format_get_nblocksx(src->format, dst_x);
src_y = util_format_get_nblocksy(src->format, src_box->y);
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
- dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
- src_pitch = rsrc->surface.level[src_level].pitch_bytes;
+ dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
+ src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
/* FIXME evergreen can do partial blit */
goto fallback;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 737d770..ba97490 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2940,22 +2940,22 @@ static void r600_dma_copy(struct pipe_context *ctx,
!r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
dstz, rsrc, src_level, src_box))
goto fallback;
src_x = util_format_get_nblocksx(src->format, src_box->x);
dst_x = util_format_get_nblocksx(src->format, dst_x);
src_y = util_format_get_nblocksy(src->format, src_box->y);
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
- dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
- src_pitch = rsrc->surface.level[src_level].pitch_bytes;
+ dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
+ src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
/* strict requirement on r6xx/r7xx */
goto fallback;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 364ed40..065d075 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -175,22 +175,23 @@ static void r600_copy_from_staging_texture(struct
pipe_context *ctx, struct r600
rctx->dma_copy(ctx, dst, transfer->level,
transfer->box.x, transfer->box.y, transfer->box.z,
src, 0, &sbox);
}
static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned
level,
const struct pipe_box *box)
{
return rtex->surface.level[level].offset +
box->z * rtex->surface.level[level].slice_size +
- box->y / rtex->surface.blk_h *
rtex->surface.level[level].pitch_bytes +
- box->x / rtex->surface.blk_w * rtex->surface.bpe;
+ (box->y / rtex->surface.blk_h *
+ rtex->surface.level[level].nblk_x +
+ box->x / rtex->surface.blk_w) * rtex->surface.bpe;
}
static int r600_init_surface(struct r600_common_screen *rscreen,
struct radeon_surf *surface,
const struct pipe_resource *ptex,
enum radeon_surf_mode array_mode,
unsigned pitch_in_bytes_override,
unsigned offset,
bool is_imported,
bool is_scanout,
@@ -252,26 +253,26 @@ static int r600_init_surface(struct r600_common_screen
*rscreen,
if (is_imported)
flags |= RADEON_SURF_IMPORTED;
r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
array_mode, surface);
if (r) {
return r;
}
- if (pitch_in_bytes_override && pitch_in_bytes_override !=
surface->level[0].pitch_bytes) {
+ if (pitch_in_bytes_override &&
+ pitch_in_bytes_override != surface->level[0].nblk_x * bpe) {
/* old ddx on evergreen over estimate alignment for 1d, only 1
level
* for those
*/
surface->level[0].nblk_x = pitch_in_bytes_override / bpe;
- surface->level[0].pitch_bytes = pitch_in_bytes_override;
surface->level[0].slice_size = pitch_in_bytes_override *
surface->level[0].nblk_y;
}
if (offset) {
for (i = 0; i < ARRAY_SIZE(surface->level); ++i)
surface->level[i].offset += offset;
}
return 0;
}
@@ -284,21 +285,21 @@ static void r600_texture_init_metadata(struct
r600_texture *rtex,
metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
metadata->pipe_config = surface->pipe_config;
metadata->bankw = surface->bankw;
metadata->bankh = surface->bankh;
metadata->tile_split = surface->tile_split;
metadata->mtilea = surface->mtilea;
metadata->num_banks = surface->num_banks;
- metadata->stride = surface->level[0].pitch_bytes;
+ metadata->stride = surface->level[0].nblk_x * surface->bpe;
metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
}
static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen)
{
p_atomic_inc(&rscreen->dirty_fb_counter);
}
static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
struct r600_texture *rtex)
@@ -541,21 +542,22 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
*/
res->external_usage |= usage &
~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
res->external_usage &=
~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
} else {
res->is_shared = true;
res->external_usage = usage;
}
return rscreen->ws->buffer_get_handle(res->buf,
-
rtex->surface.level[0].pitch_bytes,
+ rtex->surface.level[0].nblk_x *
+ rtex->surface.bpe,
rtex->surface.level[0].offset,
rtex->surface.level[0].slice_size,
whandle);
}
static void r600_texture_destroy(struct pipe_screen *screen,
struct pipe_resource *ptex)
{
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = &rtex->resource;
@@ -938,48 +940,46 @@ void r600_print_texture_info(struct r600_texture *rtex,
FILE *f)
fprintf(f, " DCCLevel[%i]: enabled=%u,
offset=%"PRIu64", "
"fast_clear_size=%"PRIu64"\n",
i, i < rtex->surface.num_dcc_levels,
rtex->surface.level[i].dcc_offset,
rtex->surface.level[i].dcc_fast_clear_size);
}
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, " Level[%i]: offset=%"PRIu64",
slice_size=%"PRIu64", "
"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u,
"
- "pitch_bytes=%u, mode=%u, tiling_index = %u\n",
+ "mode=%u, tiling_index = %u\n",
i, rtex->surface.level[i].offset,
rtex->surface.level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.height0, i),
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.level[i].nblk_x,
rtex->surface.level[i].nblk_y,
- rtex->surface.level[i].pitch_bytes,
rtex->surface.level[i].mode,
rtex->surface.tiling_index[i]);
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
fprintf(f, " StencilLayout: tilesplit=%u\n",
rtex->surface.stencil_tile_split);
for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
"slice_size=%"PRIu64", npix_x=%u, "
"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
- "pitch_bytes=%u, mode=%u, tiling_index = %u\n",
+ "mode=%u, tiling_index = %u\n",
i, rtex->surface.stencil_level[i].offset,
rtex->surface.stencil_level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.height0, i),
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.stencil_level[i].nblk_x,
rtex->surface.stencil_level[i].nblk_y,
- rtex->surface.stencil_level[i].pitch_bytes,
rtex->surface.stencil_level[i].mode,
rtex->surface.stencil_tiling_index[i]);
}
}
}
/* Common processing for r600_texture_create and r600_texture_from_handle */
static struct r600_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
@@ -1540,53 +1540,56 @@ static void *r600_texture_transfer_map(struct
pipe_context *ctx,
}
rctx->blit_decompress_depth(ctx, rtex, staging_depth,
level, level,
box->z, box->z + box->depth
- 1,
0, 0);
offset = r600_texture_get_offset(staging_depth, level,
box);
}
- trans->transfer.stride =
staging_depth->surface.level[level].pitch_bytes;
+ trans->transfer.stride =
staging_depth->surface.level[level].nblk_x *
+ staging_depth->surface.bpe;
trans->transfer.layer_stride =
staging_depth->surface.level[level].slice_size;
trans->staging = (struct r600_resource*)staging_depth;
buf = trans->staging;
} else if (use_staging_texture) {
struct pipe_resource resource;
struct r600_texture *staging;
r600_init_temp_resource_from_box(&resource, texture, box, level,
R600_RESOURCE_FLAG_TRANSFER);
resource.usage = (usage & PIPE_TRANSFER_READ) ?
PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
/* Create the temporary texture. */
staging = (struct
r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
if (!staging) {
R600_ERR("failed to create temporary texture to hold
untiled copy\n");
FREE(trans);
return NULL;
}
trans->staging = &staging->resource;
- trans->transfer.stride = staging->surface.level[0].pitch_bytes;
+ trans->transfer.stride = staging->surface.level[0].nblk_x *
+ staging->surface.bpe;
trans->transfer.layer_stride =
staging->surface.level[0].slice_size;
if (usage & PIPE_TRANSFER_READ)
r600_copy_to_staging_texture(ctx, trans);
else
usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
buf = trans->staging;
} else {
/* the resource is mapped directly */
- trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
+ trans->transfer.stride = rtex->surface.level[level].nblk_x *
+ rtex->surface.bpe;
trans->transfer.layer_stride =
rtex->surface.level[level].slice_size;
offset = r600_texture_get_offset(rtex, level, box);
buf = &rtex->resource;
}
if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
r600_resource_reference(&trans->staging, NULL);
FREE(trans);
return NULL;
}
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index fb1491a..93fe147 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -1346,21 +1346,21 @@ static unsigned bank_wh(unsigned bankwh)
}
return bankwh;
}
/**
* fill decoding target field from the luma and chroma surfaces
*/
void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
struct radeon_surf *chroma)
{
- msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
+ msg->body.decode.dt_pitch = luma->level[0].nblk_x * luma->bpe;
switch (luma->level[0].mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
break;
case RADEON_SURF_MODE_1D:
msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
break;
case RADEON_SURF_MODE_2D:
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index 7e7bf2a..2f50ef4 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -216,21 +216,21 @@ struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
{
return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next,
list);
}
/**
* Calculate the offsets into the CPB
*/
void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
signed *luma_offset, signed *chroma_offset)
{
- unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
+ unsigned pitch = align(enc->luma->level[0].nblk_x * enc->luma->bpe,
128);
unsigned vpitch = align(enc->luma->level[0].nblk_y, 16);
unsigned fsize = pitch * (vpitch + vpitch / 2);
*luma_offset = slot->index * fsize;
*chroma_offset = *luma_offset + pitch * vpitch;
}
/**
* destroy this video encoder
*/
@@ -447,21 +447,21 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
RVID_ERR("Can't create video buffer.\n");
goto error;
}
enc->cpb_num = get_cpb_num(enc);
if (!enc->cpb_num)
goto error;
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL,
&tmp_surf);
- cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
+ cpb_size = align(tmp_surf->level[0].nblk_x * tmp_surf->bpe, 128);
cpb_size = cpb_size * align(tmp_surf->level[0].nblk_y, 32);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
if (enc->dual_pipe)
cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
tmp_buf->destroy(tmp_buf);
if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't create CPB buffer.\n");
goto error;
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index f194063..358c0fc 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -87,22 +87,22 @@ static void create(struct rvce_encoder *enc)
enc->task_info(enc, 0x00000000, 0, 0, 0);
RVCE_BEGIN(0x01000001); // create cmd
RVCE_CS(0x00000000); // encUseCircularBuffer
RVCE_CS(profiles[enc->base.profile -
PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(0x00000000); // encPicStructRestriction
RVCE_CS(enc->base.width); // encImageWidth
RVCE_CS(enc->base.height); // encImageHeight
- RVCE_CS(enc->luma->level[0].pitch_bytes); // encRefPicLumaPitch
- RVCE_CS(enc->chroma->level[0].pitch_bytes); // encRefPicChromaPitch
+ RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); //
encRefPicLumaPitch
+ RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); //
encRefPicChromaPitch
RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(0x00000000); // encRefPic(Addr|Array)Mode,
encPicStructRestriction, disableRDO
RVCE_END();
}
static void rate_control(struct rvce_encoder *enc)
{
RVCE_BEGIN(0x04000005); // rate control
RVCE_CS(enc->pic.rate_ctrl.rate_ctrl_method); // encRateControlMethod
RVCE_CS(enc->pic.rate_ctrl.target_bitrate); //
encRateControlTargetBitRate
@@ -317,22 +317,22 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
RVCE_CS(0x00000000); // forceRefreshMap
RVCE_CS(0x00000000); // insertAUD
RVCE_CS(0x00000000); // endOfSequence
RVCE_CS(0x00000000); // endOfStream
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); //
inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
- RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
- RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
+ RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); //
encInputPicLumaPitch
+ RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); //
encInputPicChromaPitch
RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode
RVCE_CS(0x00000000); // encInputPicTileConfig
RVCE_CS(enc->pic.picture_type); // encPicType
RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); //
encIdrFlag
RVCE_CS(0x00000000); // encIdrPicId
RVCE_CS(0x00000000); // encMGSKeyPic
RVCE_CS(!enc->pic.not_referenced); // encReferenceFlag
RVCE_CS(0x00000000); // encTemporalLayerIndex
RVCE_CS(0x00000000); // num_ref_idx_active_override_flag
RVCE_CS(0x00000000); // num_ref_idx_l0_active_minus1
diff --git a/src/gallium/drivers/radeon/radeon_vce_50.c
b/src/gallium/drivers/radeon/radeon_vce_50.c
index a2877f8..f19202e 100644
--- a/src/gallium/drivers/radeon/radeon_vce_50.c
+++ b/src/gallium/drivers/radeon/radeon_vce_50.c
@@ -124,22 +124,22 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
RVCE_CS(0x00000000); // forceRefreshMap
RVCE_CS(0x00000000); // insertAUD
RVCE_CS(0x00000000); // endOfSequence
RVCE_CS(0x00000000); // endOfStream
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
- RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
- RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
+ RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); //
encInputPicLumaPitch
+ RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); //
encInputPicChromaPitch
if (enc->dual_pipe)
RVCE_CS(0x00000000); //
encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
else
RVCE_CS(0x00010000); //
encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
RVCE_CS(0x00000000); // encInputPicTileConfig
RVCE_CS(enc->pic.picture_type); // encPicType
RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); //
encIdrFlag
RVCE_CS(0x00000000); // encIdrPicId
RVCE_CS(0x00000000); // encMGSKeyPic
RVCE_CS(!enc->pic.not_referenced); // encReferenceFlag
diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c
b/src/gallium/drivers/radeon/radeon_vce_52.c
index 0922f13..e8a961f 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -170,22 +170,22 @@ static void create(struct rvce_encoder *enc)
enc->task_info(enc, 0x00000000, 0, 0, 0);
RVCE_BEGIN(0x01000001); // create cmd
RVCE_CS(enc->enc_pic.ec.enc_use_circular_buffer);
RVCE_CS(profiles[enc->base.profile -
PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(enc->enc_pic.ec.enc_pic_struct_restriction);
RVCE_CS(enc->base.width); // encImageWidth
RVCE_CS(enc->base.height); // encImageHeight
- RVCE_CS(enc->luma->level[0].pitch_bytes); // encRefPicLumaPitch
- RVCE_CS(enc->chroma->level[0].pitch_bytes); // encRefPicChromaPitch
+ RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); //
encRefPicLumaPitch
+ RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); //
encRefPicChromaPitch
RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(enc->enc_pic.addrmode_arraymode_disrdo_distwoinstants);
RVCE_CS(enc->enc_pic.ec.enc_pre_encode_context_buffer_offset);
RVCE_CS(enc->enc_pic.ec.enc_pre_encode_input_luma_buffer_offset);
RVCE_CS(enc->enc_pic.ec.enc_pre_encode_input_chroma_buffer_offset);
RVCE_CS(enc->enc_pic.ec.enc_pre_encode_mode_chromaflag_vbaqmode_scenechangesensitivity);
RVCE_END();
}
@@ -237,22 +237,22 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
RVCE_CS(enc->enc_pic.eo.force_refresh_map);
RVCE_CS(enc->enc_pic.eo.insert_aud);
RVCE_CS(enc->enc_pic.eo.end_of_sequence);
RVCE_CS(enc->enc_pic.eo.end_of_stream);
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
- RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
- RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
+ RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); //
encInputPicLumaPitch
+ RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); //
encInputPicChromaPitch
if (enc->dual_pipe)
enc->enc_pic.eo.enc_input_pic_addr_array_disable2pipe_disablemboffload =
0x00000000;
else
enc->enc_pic.eo.enc_input_pic_addr_array_disable2pipe_disablemboffload =
0x00010000;
RVCE_CS(enc->enc_pic.eo.enc_input_pic_addr_array_disable2pipe_disablemboffload);
RVCE_CS(enc->enc_pic.eo.enc_input_pic_tile_config);
RVCE_CS(enc->enc_pic.picture_type); // encPicType
RVCE_CS(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR);
// encIdrFlag
if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR) &&
(enc->enc_pic.eo.enc_idr_pic_id !=0))
enc->enc_pic.eo.enc_idr_pic_id = enc->enc_pic.idr_pic_id - 1;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index f5b9f10..1e7035f 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -274,21 +274,20 @@ enum radeon_surf_mode {
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_IMPORTED (1 << 24)
struct radeon_surf_level {
uint64_t offset;
uint64_t slice_size;
uint64_t dcc_offset;
uint64_t dcc_fast_clear_size;
uint16_t nblk_x;
uint16_t nblk_y;
- uint32_t pitch_bytes;
enum radeon_surf_mode mode;
};
struct radeon_surf {
/* Format properties. */
unsigned blk_w:4;
unsigned blk_h:4;
unsigned bpe:5;
/* Number of mipmap levels where DCC is enabled starting from level 0.
* Non-zero levels may be disabled due to alignment constraints, but not
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c
b/src/gallium/drivers/radeonsi/cik_sdma.c
index 338c0cf..b3eaed5 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -127,22 +127,22 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
uint64_t src_address = rsrc->resource.gpu_address +
rsrc->surface.level[src_level].offset;
unsigned dst_mode = rdst->surface.level[dst_level].mode;
unsigned src_mode = rsrc->surface.level[src_level].mode;
unsigned dst_tile_index = rdst->surface.tiling_index[dst_level];
unsigned src_tile_index = rsrc->surface.tiling_index[src_level];
unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
- unsigned dst_pitch = rdst->surface.level[dst_level].pitch_bytes / bpp;
- unsigned src_pitch = rsrc->surface.level[src_level].pitch_bytes / bpp;
+ unsigned dst_pitch = rdst->surface.level[dst_level].nblk_x;
+ unsigned src_pitch = rsrc->surface.level[src_level].nblk_x;
uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size /
bpp;
uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size /
bpp;
unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,
dst_level, rdst->surface.blk_w);
unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0,
src_level, rsrc->surface.blk_w);
unsigned dst_height = minify_as_blocks(rdst->resource.b.b.height0,
dst_level, rdst->surface.blk_h);
unsigned src_height = minify_as_blocks(rsrc->resource.b.b.height0,
src_level, rsrc->surface.blk_h);
diff --git a/src/gallium/drivers/radeonsi/si_dma.c
b/src/gallium/drivers/radeonsi/si_dma.c
index 6bbb5d6..dee5ec5 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -225,22 +225,22 @@ static void si_dma_copy(struct pipe_context *ctx,
!r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
dstz, rsrc, src_level, src_box))
goto fallback;
src_x = util_format_get_nblocksx(src->format, src_box->x);
dst_x = util_format_get_nblocksx(src->format, dst_x);
src_y = util_format_get_nblocksy(src->format, src_box->y);
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
- dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
- src_pitch = rsrc->surface.level[src_level].pitch_bytes;
+ dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
+ src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
src_box->width != src_w ||
src_box->height != u_minify(rsrc->resource.b.b.height0, src_level)
||
src_box->height != u_minify(rdst->resource.b.b.height0, dst_level)
||
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 8c57287..deae4dd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -184,21 +184,20 @@ static int compute_level(struct amdgpu_winsys *ws,
ret = AddrComputeSurfaceInfo(ws->addrlib,
AddrSurfInfoIn,
AddrSurfInfoOut);
if (ret != ADDR_OK) {
return ret;
}
surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
- surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 :
surf->bpe);
surf_level->nblk_x = AddrSurfInfoOut->pitch;
surf_level->nblk_y = AddrSurfInfoOut->height;
switch (AddrSurfInfoOut->tileMode) {
case ADDR_TM_LINEAR_ALIGNED:
surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
break;
case ADDR_TM_1D_TILED_THIN1:
surf_level->mode = RADEON_SURF_MODE_1D;
break;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index fed96ee..95ec0eb 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -60,39 +60,41 @@ static void set_micro_tile_mode(struct radeon_surf *surf,
tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
}
static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
- const struct radeon_surf_level *level_ws)
+ const struct radeon_surf_level *level_ws,
+ unsigned bpe)
{
level_drm->offset = level_ws->offset;
level_drm->slice_size = level_ws->slice_size;
level_drm->nblk_x = level_ws->nblk_x;
level_drm->nblk_y = level_ws->nblk_y;
- level_drm->pitch_bytes = level_ws->pitch_bytes;
+ level_drm->pitch_bytes = level_ws->nblk_x * bpe;
level_drm->mode = level_ws->mode;
}
static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws,
- const struct radeon_surface_level
*level_drm)
+ const struct radeon_surface_level
*level_drm,
+ unsigned bpe)
{
level_ws->offset = level_drm->offset;
level_ws->slice_size = level_drm->slice_size;
level_ws->nblk_x = level_drm->nblk_x;
level_ws->nblk_y = level_drm->nblk_y;
- level_ws->pitch_bytes = level_drm->pitch_bytes;
level_ws->mode = level_drm->mode;
+ assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
}
static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
const struct pipe_resource *tex,
unsigned flags, unsigned bpe,
enum radeon_surf_mode mode,
const struct radeon_surf *surf_ws)
{
int i;
@@ -149,23 +151,23 @@ static void surf_winsys_to_drm(struct radeon_surface
*surf_drm,
surf_drm->bo_size = surf_ws->surf_size;
surf_drm->bo_alignment = surf_ws->surf_alignment;
surf_drm->bankw = surf_ws->bankw;
surf_drm->bankh = surf_ws->bankh;
surf_drm->mtilea = surf_ws->mtilea;
surf_drm->tile_split = surf_ws->tile_split;
surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
- surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
+ surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i], bpe);
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
- &surf_ws->stencil_level[i]);
+ &surf_ws->stencil_level[i], bpe);
surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
}
}
static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
struct radeon_surf *surf_ws,
const struct radeon_surface *surf_drm)
{
@@ -183,23 +185,24 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys
*ws,
surf_ws->bankw = surf_drm->bankw;
surf_ws->bankh = surf_drm->bankh;
surf_ws->mtilea = surf_drm->mtilea;
surf_ws->tile_split = surf_drm->tile_split;
surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
- surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
+ surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i],
+ surf_drm->bpe * surf_drm->nsamples);
surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
- &surf_drm->stencil_level[i]);
+ &surf_drm->stencil_level[i],
surf_drm->nsamples);
surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
}
set_micro_tile_mode(surf_ws, &ws->info);
}
static int radeon_winsys_surface_init(struct radeon_winsys *rws,
const struct pipe_resource *tex,
--
2.7.4
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