From: Marek Olšák <[email protected]>
---
src/gallium/drivers/radeon/r600_texture.c | 10 +++++-----
src/gallium/drivers/radeon/radeon_winsys.h | 8 ++++++++
src/gallium/drivers/radeonsi/si_blit.c | 3 +--
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 7ced41c..6933304 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2340,49 +2340,49 @@ static void si_set_optimal_micro_tile_mode(struct
r600_common_screen *rscreen,
assert(rtex->surface.level[0].mode == RADEON_SURF_MODE_2D);
assert(rtex->resource.b.b.last_level == 0);
/* These magic numbers were copied from addrlib. It doesn't use any
* definitions for them either. They are all 2D_TILED_THIN1 modes with
* different bpp and micro tile mode.
*/
if (rscreen->chip_class >= CIK) {
switch (rtex->last_msaa_resolve_target_micro_mode) {
- case 0: /* displayable */
+ case RADEON_MICRO_MODE_DISPLAY:
rtex->surface.tiling_index[0] = 10;
break;
- case 1: /* thin */
+ case RADEON_MICRO_MODE_THIN:
rtex->surface.tiling_index[0] = 14;
break;
- case 3: /* rotated */
+ case RADEON_MICRO_MODE_ROTATED:
rtex->surface.tiling_index[0] = 28;
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
return;
}
} else { /* SI */
switch (rtex->last_msaa_resolve_target_micro_mode) {
- case 0: /* displayable */
+ case RADEON_MICRO_MODE_DISPLAY:
switch (rtex->surface.bpe) {
case 1:
rtex->surface.tiling_index[0] = 10;
break;
case 2:
rtex->surface.tiling_index[0] = 11;
break;
default: /* 4, 8 */
rtex->surface.tiling_index[0] = 12;
break;
}
break;
- case 1: /* thin */
+ case RADEON_MICRO_MODE_THIN:
switch (rtex->surface.bpe) {
case 1:
rtex->surface.tiling_index[0] = 14;
break;
case 2:
rtex->surface.tiling_index[0] = 15;
break;
case 4:
rtex->surface.tiling_index[0] = 16;
break;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index f65f669..3e30e95 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -256,20 +256,28 @@ enum radeon_feature_id {
};
#define RADEON_SURF_MAX_LEVELS 15
enum radeon_surf_mode {
RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
RADEON_SURF_MODE_1D = 2,
RADEON_SURF_MODE_2D = 3,
};
+/* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
+enum radeon_micro_mode {
+ RADEON_MICRO_MODE_DISPLAY = 0,
+ RADEON_MICRO_MODE_THIN = 1,
+ RADEON_MICRO_MODE_DEPTH = 2,
+ RADEON_MICRO_MODE_ROTATED = 3,
+};
+
/* the first 16 bits are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_SCANOUT (1 << 16)
#define RADEON_SURF_ZBUFFER (1 << 17)
#define RADEON_SURF_SBUFFER (1 << 18)
#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER |
RADEON_SURF_SBUFFER)
/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_IMPORTED (1 << 24)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 0fd1106..e086ed8 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -15,21 +15,20 @@
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "si_pipe.h"
-#include "sid.h"
#include "util/u_format.h"
#include "util/u_surface.h"
enum si_blitter_op /* bitmask */
{
SI_SAVE_TEXTURES = 1,
SI_SAVE_FRAMEBUFFER = 2,
SI_SAVE_FRAGMENT_STATE = 4,
SI_DISABLE_RENDER_COND = 8,
@@ -1058,21 +1057,21 @@ resolve_to_temp:
templ.format = info->src.resource->format;
templ.width0 = info->src.resource->width0;
templ.height0 = info->src.resource->height0;
templ.depth0 = 1;
templ.array_size = 1;
templ.usage = PIPE_USAGE_DEFAULT;
templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
R600_RESOURCE_FLAG_DISABLE_DCC;
/* The src and dst microtile modes must be the same. */
- if (src->surface.micro_tile_mode ==
V_009910_ADDR_SURF_DISPLAY_MICRO_TILING)
+ if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
templ.bind = PIPE_BIND_SCANOUT;
else
templ.bind = 0;
tmp = ctx->screen->resource_create(ctx->screen, &templ);
if (!tmp)
return false;
assert(src->surface.micro_tile_mode ==
((struct r600_texture*)tmp)->surface.micro_tile_mode);
--
2.7.4
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