================
@@ -4069,6 +4069,22 @@ let Predicates = [HasSVE2_or_SME] in {
let AddedComplexity = 2 in {
def : Pat<(nxv16i8 (AArch64ext nxv16i8:$zn1, nxv16i8:$zn2, (i32
imm0_255:$imm))),
(EXT_ZZI_B (REG_SEQUENCE ZPR2, $zn1, zsub0, $zn2, zsub1),
imm0_255:$imm)>;
+
+ foreach VT = [nxv16i8] in
+ def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_255
i32:$index)))),
+ (EXT_ZZI_B (REG_SEQUENCE ZPR2, $Z1, zsub0, $Z2, zsub1),
imm0_255:$index)>;
----------------
sdesmalen-arm wrote:
Why does this result in different output as the pattern above? is this because
of the change you've made in #151729?
I would actually expect `vector_splice` and `AArch64ISD::EXT` to have the same
semantics (and if there isn't some subtle difference between `AArch64ISD::EXT`
and `ISD::VECTOR_SPLICE`, then I think we should remove the former)
https://github.com/llvm/llvm-project/pull/151730
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