https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/146004
Backport a19ddff980136835fead07b346bd83e9211124a0 30e519e1ad185701eb9593f6c727c808d7590d1b Requested by: @zhaoqi5 >From 85a89d657a7ab6bb12e11b288a3c72019e3424b3 Mon Sep 17 00:00:00 2001 From: Qi Zhao <zhaoq...@loongson.cn> Date: Thu, 26 Jun 2025 18:42:25 +0800 Subject: [PATCH 1/2] [LoongArch] Pre-commit test for fixing xvshuf instructions. NFC For this test, the `xvshuf.d` instruction should not be generated. This will be fixed later. (cherry picked from commit a19ddff980136835fead07b346bd83e9211124a0) --- .../LoongArch/lasx/ir-instruction/fix-xvshuf.ll | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll new file mode 100644 index 0000000000000..21067031cb7bb --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll @@ -0,0 +1,17 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s + +;; Fix https://github.com/llvm/llvm-project/issues/137000. + +define <4 x double> @shufflevector_v4f64(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: shufflevector_v4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0) +; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI0_0) +; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0 +; CHECK-NEXT: xvori.b $xr0, $xr2, 0 +; CHECK-NEXT: ret +entry: + %c = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 6, i32 3, i32 7> + ret <4 x double> %c +} >From 212ac53200e08814b22fee60779adc8bffab29c2 Mon Sep 17 00:00:00 2001 From: ZhaoQi <zhaoq...@loongson.cn> Date: Fri, 27 Jun 2025 10:29:32 +0800 Subject: [PATCH 2/2] [LoongArch] Fix xvshuf instructions lowering (#145868) Fix https://github.com/llvm/llvm-project/issues/137000. (cherry picked from commit 30e519e1ad185701eb9593f6c727c808d7590d1b) --- .../LoongArch/LoongArchISelLowering.cpp | 2 +- .../lasx/ir-instruction/fix-xvshuf.ll | 19 ++++++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 4ed3c3cf92e3e..98b7a1126e560 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -1209,7 +1209,7 @@ static SDValue lowerVECTOR_SHUFFLE_XVSHUF(const SDLoc &DL, ArrayRef<int> Mask, if (*it < 0) // UNDEF MaskAlloc.push_back(DAG.getTargetConstant(0, DL, MVT::i64)); else if ((*it >= 0 && *it < HalfSize) || - (*it >= MaskSize && *it <= MaskSize + HalfSize)) { + (*it >= MaskSize && *it < MaskSize + HalfSize)) { int M = *it < HalfSize ? *it : *it - HalfSize; MaskAlloc.push_back(DAG.getTargetConstant(M, DL, MVT::i64)); } else diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll index 21067031cb7bb..f3bec11810e9b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll @@ -6,9 +6,22 @@ define <4 x double> @shufflevector_v4f64(<4 x double> %a, <4 x double> %b) { ; CHECK-LABEL: shufflevector_v4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0) -; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI0_0) -; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0 +; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 0 +; CHECK-NEXT: movgr2fr.d $fa2, $a0 +; CHECK-NEXT: xvpickve2gr.d $a0, $xr1, 2 +; CHECK-NEXT: movgr2fr.d $fa3, $a0 +; CHECK-NEXT: movfr2gr.d $a0, $fa2 +; CHECK-NEXT: xvinsgr2vr.d $xr2, $a0, 0 +; CHECK-NEXT: movfr2gr.d $a0, $fa3 +; CHECK-NEXT: xvinsgr2vr.d $xr2, $a0, 1 +; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 3 +; CHECK-NEXT: movgr2fr.d $fa0, $a0 +; CHECK-NEXT: xvpickve2gr.d $a0, $xr1, 3 +; CHECK-NEXT: movgr2fr.d $fa1, $a0 +; CHECK-NEXT: movfr2gr.d $a0, $fa0 +; CHECK-NEXT: xvinsgr2vr.d $xr2, $a0, 2 +; CHECK-NEXT: movfr2gr.d $a0, $fa1 +; CHECK-NEXT: xvinsgr2vr.d $xr2, $a0, 3 ; CHECK-NEXT: xvori.b $xr0, $xr2, 0 ; CHECK-NEXT: ret entry: _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
