================
@@ -69,3 +72,37 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI,
Register Reg,
return std::pair(Reg, 0);
}
+
+IntrinsicLaneMaskAnalyzer::IntrinsicLaneMaskAnalyzer(MachineFunction &MF)
+ : MRI(MF.getRegInfo()) {
+ initLaneMaskIntrinsics(MF);
+}
+
+bool IntrinsicLaneMaskAnalyzer::isS32S64LaneMask(Register Reg) const {
+ return S32S64LaneMask.contains(Reg);
+}
+
+void IntrinsicLaneMaskAnalyzer::initLaneMaskIntrinsics(MachineFunction &MF) {
+ for (auto &MBB : MF) {
+ for (auto &MI : MBB) {
+ GIntrinsic *GI = dyn_cast<GIntrinsic>(&MI);
+ if (GI && GI->is(Intrinsic::amdgcn_if_break)) {
+ S32S64LaneMask.insert(MI.getOperand(3).getReg());
+ findLCSSAPhi(MI.getOperand(0).getReg());
+ }
+
+ if (MI.getOpcode() == AMDGPU::SI_IF ||
+ MI.getOpcode() == AMDGPU::SI_ELSE) {
+ findLCSSAPhi(MI.getOperand(0).getReg());
+ }
----------------
arsenm wrote:
I don't understand why you are mixing matching the intrinsic form of if.break
above, but the selected pseudos for if and else
https://github.com/llvm/llvm-project/pull/112863
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