Author: Jun Ma Date: 2021-12-17T10:30:02+08:00 New Revision: eb64afdb5c50932d271952538a4778849029a68d
URL: https://github.com/llvm/llvm-project/commit/eb64afdb5c50932d271952538a4778849029a68d DIFF: https://github.com/llvm/llvm-project/commit/eb64afdb5c50932d271952538a4778849029a68d.diff LOG: [RISCV] Add N3 Load/Store under Xin Added: llvm/lib/Target/RISCV/RISCVInstrInfoXin.td Modified: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/RISCVInstrFormats.td llvm/lib/Target/RISCV/RISCVInstrInfo.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 75592dd4c6f54..d54faba4315a6 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -669,6 +669,14 @@ struct RISCVOperand : public MCParsedAsmOperand { VK == RISCVMCExpr::VK_RISCV_None; } + bool isSImm10Lsb000() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedInt<7, 3>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isUImm20LUI() const { RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; int64_t Imm; diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index 6a16b6354f954..bcb6413a17ad0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -145,6 +145,7 @@ def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>; def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>; def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>; def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>; +def OPC_CUSTOM1 : RISCVOpcode<"CUSTOM1", 0b0001011>; class RVInst<dag outs, dag ins, string opcodestr, string argstr, list<dag> pattern, InstFormat format> diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 71eb6f01a4f42..1db89b71af294 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1478,3 +1478,4 @@ include "RISCVInstrInfoC.td" include "RISCVInstrInfoZb.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZfh.td" +include "RISCVInstrInfoXin.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXin.td new file mode 100644 index 0000000000000..eed9e8fab6a3f --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXin.td @@ -0,0 +1,90 @@ +//===-- RISCVInstrInfoXin.td - Target Description for Xin ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the Xin instructions in TableGen format. +// +//===----------------------------------------------------------------------===// + + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +// A 10-bit signed immediate where the least significant three bits are zero. +def simm10_lsb000: Operand<XLenVT>, + ImmLeaf<XLenVT, + [{return isShiftedInt<7, 4>(Imm);}]> { + let ParserMatchClass = SImmAsmOperand<10, "Lsb000">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeSImmOperand<10>"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedInt<7, 3>(Imm); + }]; +} + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class RVXinLoadPair<bits<3> funct3, string opcodestr> + : RVInstR<0, funct3, OPC_CUSTOM1, + (outs GPR:$rd, GPR:$rs2), (ins GPR:$rs1, simm10_lsb000:$imm), + opcodestr, "$rd, $rs2, ${imm}(${rs1})"> { + bits<10> imm; + let Inst{31-25} = imm{9-3}; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +class RVXinStorePair<bits<3> funct3, string opcodestr> + : RVInstR<0, funct3, OPC_CUSTOM1, + (outs), (ins GPR:$rd, GPR:$rs2, GPR:$rs1, simm10_lsb000:$imm), + opcodestr, "$rd, $rs2, ${imm}(${rs1})"> { + bits<10> imm; + let Inst{31-25} = imm{9-3}; +} + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class RVXinLoadReg<bits<7> funct7, bits<3> funct3, string opcodestr> + : RVInstR<funct7, funct3, OPC_CUSTOM1, + (outs GPR:$rd), (ins GPR:$rs2, GPR: $rs1), + opcodestr, "$rd, $rs2, $rs1">; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +class RVXinStoreReg<bits<7> funct7, bits<3> funct3, string opcodestr> + : RVInstR<funct7, funct3, OPC_CUSTOM1, + (outs), (ins GPR:$rd, GPR:$rs2, GPR:$rs1), + opcodestr, "$rd, $rs2, $rs1">; + +let Predicates = [HasStdExtXin, IsRV64] in { +def LDP : RVXinLoadPair<0b000, "ldp">; +def SDP : RVXinStorePair<0b001, "sdp">; + +def LBR : RVXinLoadReg<0b0000000, 0b010, "lbr">; +def LBRU : RVXinLoadReg<0b0000000, 0b110, "lbru">; +def LHR : RVXinLoadReg<0b0100000, 0b010, "lhr">; +def LHRU : RVXinLoadReg<0b0100000, 0b110, "lhru">; +def LHRS : RVXinLoadReg<0b0110000, 0b010, "lhrs">; +def LHRSU : RVXinLoadReg<0b0110000, 0b110, "lhrsu">; +def LWR : RVXinLoadReg<0b1000000, 0b010, "lwr">; +def LWRU : RVXinLoadReg<0b1000000, 0b110, "lwru">; +def LWRS : RVXinLoadReg<0b1010000, 0b010, "lwrs">; +def LWRSU : RVXinLoadReg<0b1010000, 0b110, "lwrsu">; +def LDR : RVXinLoadReg<0b1100000, 0b010, "ldr">; +def LDRS : RVXinLoadReg<0b1110000, 0b010, "ldrs">; + +def SBR : RVXinStoreReg<0b0000000, 0b011, "sbr">; +def SHR : RVXinStoreReg<0b0100000, 0b011, "shr">; +def SHRS : RVXinStoreReg<0b0110000, 0b011, "shrs">; +def SWR : RVXinStoreReg<0b1000000, 0b011, "swr">; +def SWRS : RVXinStoreReg<0b1010000, 0b011, "swrs">; +def SDR : RVXinStoreReg<0b1100000, 0b011, "sdr">; +def SDRS : RVXinStoreReg<0b1110000, 0b011, "sdrs">; +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
