Author: Jun Ma Date: 2021-12-17T10:30:02+08:00 New Revision: 402aaf7d3f6d48e023b0aa6005c439a18cd4d029
URL: https://github.com/llvm/llvm-project/commit/402aaf7d3f6d48e023b0aa6005c439a18cd4d029 DIFF: https://github.com/llvm/llvm-project/commit/402aaf7d3f6d48e023b0aa6005c439a18cd4d029.diff LOG: [RISCV] Add non-standard Xin feature for N3 core Added: Modified: clang/test/Driver/riscv-arch.c clang/test/Preprocessor/riscv-target-features.c llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfoZb.td llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/test/CodeGen/RISCV/select-bare.ll llvm/test/MC/RISCV/attribute-arch.s Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 5b99643309a57..8866d9301b545 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -472,3 +472,12 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s // RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg" + +// RUN: %clang -target riscv32-unknown-elf -march=rv32ixin -### %s \ +// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-XIN-NOFLAG %s +// RV32-EXPERIMENTAL-XIN-NOFLAG: error: invalid arch name 'rv32ixin' +// RV32-EXPERIMENTAL-XIN-NOFLAG: requires '-menable-experimental-extensions' + +// RUN: %clang -target riscv32-unknown-elf -march=rv32ixin0p1 -menable-experimental-extensions -### %s \ +// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-XIN %s +// RV32-EXPERIMENTAL-XIN: "-target-feature" "+experimental-xin" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index a0a1ac59cc4cc..14a605a7ef43c 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -33,6 +33,7 @@ // CHECK-NOT: __riscv_vector // CHECK-NOT: __riscv_zvamo // CHECK-NOT: __riscv_zvlsseg +// CHECK-NOT: __riscv_xin // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s @@ -223,3 +224,11 @@ // RUN: -march=rv64izfh0p1 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s // CHECK-ZFH-EXT: __riscv_zfh 1000 + +// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv32i_xin0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XIN-EXT %s +// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64i_xin0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XIN-EXT %s +// CHECK-XIN-EXT: __riscv_xin 1000 diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 94929e7e052f1..b4a310254db59 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -66,6 +66,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zfhmin", RISCVExtensionVersion{0, 1}}, {"zfh", RISCVExtensionVersion{0, 1}}, + + {"xin", RISCVExtensionVersion{0, 1}}, }; static bool stripExperimentalPrefix(StringRef &Ext) { diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 772a4f8ecd535..4a94581107b19 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -176,6 +176,19 @@ def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">, AssemblerPredicate<(all_of FeatureStdExtZvamo), "'Zvamo' (Vector AMO Operations)">; +def FeatureStdExtXin + : SubtargetFeature<"experimental-xin", "HasStdExtXin", "true", + "'Xin' ('N3' Instructions)">; +def HasStdExtXin : Predicate<"Subtarget->hasStdExtXin()">, + AssemblerPredicate<(all_of FeatureStdExtXin), + "'Xin' ('N3' Instructions)">; + +def HasStdExtZbtOrXin + : Predicate<"Subtarget->hasStdExtZbt() || Subtarget->hasStdExtXin()">, + AssemblerPredicate<(any_of FeatureStdExtZbt, FeatureStdExtXin), + "'Zbt' (Ternary 'B' Instructions) or " + "'Xin' ('N3' Instructions)">; + def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index f33965b504591..9c485e834b21d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -307,6 +307,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FSHL, MVT::i32, Custom); setOperationAction(ISD::FSHR, MVT::i32, Custom); } + } else if (Subtarget.hasStdExtXin()) { + setOperationAction(ISD::SELECT, XLenVT, Legal); } else { setOperationAction(ISD::SELECT, XLenVT, Custom); } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index 7eb8ae7d4193c..77bcd50e560b9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -368,11 +368,13 @@ def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>; def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>; } // Predicates = [HasStdExtZbp] +let Predicates = [HasStdExtZbtOrXin] in +def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">, + Sched<[]>; + let Predicates = [HasStdExtZbt] in { def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">, Sched<[]>; -def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">, - Sched<[]>; def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">, Sched<[]>; def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">, @@ -857,7 +859,9 @@ def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>; let Predicates = [HasStdExtZbt] in { def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)), (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; +} // Predicates = [HasStdExtZbt] +let Predicates = [HasStdExtZbtOrXin] in { def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3), (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1), @@ -880,7 +884,7 @@ def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1), (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>; def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3), (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; -} // Predicates = [HasStdExtZbt] +} // Predicates = [HasStdExtZbtOrXin] // fshl and fshr concatenate their operands in the same order. fsr and fsl // instruction use diff erent orders. fshl will return its first operand for diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index deb2a11f98f10..0fde80d060082 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -54,6 +54,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool HasStdExtZvamo = false; bool HasStdExtZfhmin = false; bool HasStdExtZfh = false; + bool HasStdExtXin = false; bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; @@ -121,6 +122,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool hasStdExtZvamo() const { return HasStdExtZvamo; } bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } bool hasStdExtZfh() const { return HasStdExtZfh; } + bool hasStdExtXin() const { return HasStdExtXin; } bool is64Bit() const { return HasRV64; } bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll index b24e1d775ffb6..c318e8fe3a34b 100644 --- a/llvm/test/CodeGen/RISCV/select-bare.ll +++ b/llvm/test/CodeGen/RISCV/select-bare.ll @@ -3,6 +3,8 @@ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IBT +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xin -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV32IBT define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind { ; RV32I-LABEL: bare_select: diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 2928222b64fff..1257657161049 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -76,3 +76,6 @@ .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10" # CHECK: attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" + +.attribute arch, "rv32ixin0p1" +# CHECK: attribute 5, "rv32i2p0_xin0p1" _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
