Author: Kazu Hirata Date: 2020-12-13T20:05:48-08:00 New Revision: ee5b5b7a35d01c8a8a08c93b0dce8b18bb8b4b39
URL: https://github.com/llvm/llvm-project/commit/ee5b5b7a35d01c8a8a08c93b0dce8b18bb8b4b39 DIFF: https://github.com/llvm/llvm-project/commit/ee5b5b7a35d01c8a8a08c93b0dce8b18bb8b4b39.diff LOG: [CodeGen] Use llvm::erase_value (NFC) Added: Modified: llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/lib/CodeGen/MachineBlockPlacement.cpp llvm/lib/CodeGen/MachineRegisterInfo.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/lib/CodeGen/TwoAddressInstructionPass.cpp Removed: ################################################################################ diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index 4ab0c60399f2..2be446531faa 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -573,7 +573,7 @@ static const DIExpression *combineDIExpressions(const DIExpression *Original, std::vector<uint64_t> Elts = Addition->getElements().vec(); // Avoid multiple DW_OP_stack_values. if (Original->isImplicit() && Addition->isImplicit()) - erase_if(Elts, [](uint64_t Op) { return Op == dwarf::DW_OP_stack_value; }); + erase_value(Elts, dwarf::DW_OP_stack_value); const DIExpression *CombinedExpr = (Elts.size() > 0) ? DIExpression::append(Original, Elts) : Original; return CombinedExpr; diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp index 61e803fbfc40..bd4640822a63 100644 --- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp +++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp @@ -3030,12 +3030,7 @@ bool MachineBlockPlacement::maybeTailDuplicateBlock( SmallVectorImpl<MachineBasicBlock *> &RemoveList = BlockWorkList; if (RemBB->isEHPad()) RemoveList = EHPadWorkList; - RemoveList.erase( - llvm::remove_if(RemoveList, - [RemBB](MachineBasicBlock *BB) { - return BB == RemBB; - }), - RemoveList.end()); + llvm::erase_value(RemoveList, RemBB); } // Handle the filter set diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index fe04ba5009bb..f5793c63acbf 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -630,8 +630,7 @@ void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { // Remove the register (and its aliases from the list). for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) - UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI), - UpdatedCSRs.end()); + llvm::erase_value(UpdatedCSRs, *AI); } const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const { diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 43dbc3df16df..0d0da6a401ba 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3510,7 +3510,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, auto &Chain = ChainNodesMatched; assert((!E || !is_contained(Chain, N)) && "Chain node replaced during MorphNode"); - Chain.erase(std::remove(Chain.begin(), Chain.end(), N), Chain.end()); + llvm::erase_value(Chain, N); }); Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo)); diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 8025851fa0f3..ecee4aed7f88 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1015,7 +1015,7 @@ bool TwoAddressInstructionPass::rescheduleKillAboveMI( if (MOReg.isPhysical() && regOverlapsSet(LiveDefs, MOReg, TRI)) return false; // Physical register def is seen. - Defs.erase(std::remove(Defs.begin(), Defs.end(), MOReg), Defs.end()); + llvm::erase_value(Defs, MOReg); } } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
