Author: hans Date: Wed Jan 24 07:33:33 2018 New Revision: 323334 URL: http://llvm.org/viewvc/llvm-project?rev=323334&view=rev Log: Merging r322372 and r322767:
------------------------------------------------------------------------ r322372 | nemanjai | 2018-01-12 15:58:41 +0100 (Fri, 12 Jan 2018) | 10 lines [PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP Part of the fix for https://bugs.llvm.org/show_bug.cgi?id=35812. This patch ensures that the compare operand for the atomic compare and swap is properly zero-extended to 32 bits if applicable. A follow-up commit will fix the extension for the SETCC node generated when expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS. That will complete the bug fix. Differential Revision: https://reviews.llvm.org/D41856 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r322767 | efriedma | 2018-01-17 23:04:36 +0100 (Wed, 17 Jan 2018) | 12 lines [LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization. The code wasn't zero-extending correctly, so the comparison could spuriously fail. Adds some AArch64 tests to cover this case. Inspired by D41791. Differential Revision: https://reviews.llvm.org/D41798 ------------------------------------------------------------------------ Added: llvm/branches/release_60/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll - copied, changed from r322372, llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll Modified: llvm/branches/release_60/ (props changed) llvm/branches/release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.h llvm/branches/release_60/lib/Target/PowerPC/PPCInstrInfo.td llvm/branches/release_60/test/CodeGen/AArch64/atomic-ops-lse.ll llvm/branches/release_60/test/CodeGen/ARM/atomic-cmpxchg.ll llvm/branches/release_60/test/CodeGen/ARM/cmpxchg-O0.ll llvm/branches/release_60/test/CodeGen/PowerPC/atomics-regression.ll Propchange: llvm/branches/release_60/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Wed Jan 24 07:33:33 2018 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321980,321991,321993-321994,322003,322053,322056,322103,322106,322223,322272,322313,322473,322623,322644,322724,322875,322878-322879,322904-322905,322973,322993,323034 +/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321980,321991,321993-321994,322003,322053,322056,322103,322106,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322904-322905,322973,322993,323034 Modified: llvm/branches/release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=323334&r1=323333&r2=323334&view=diff ============================================================================== --- llvm/branches/release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/branches/release_60/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 24 07:33:33 2018 @@ -2965,12 +2965,12 @@ bool SelectionDAGLegalize::ExpandNode(SD case ISD::ZERO_EXTEND: LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res, DAG.getValueType(AtomicType)); - RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2)); + RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); ExtRes = LHS; break; case ISD::ANY_EXTEND: LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType); - RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2)); + RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); break; default: llvm_unreachable("Invalid atomic op extension"); Modified: llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp?rev=323334&r1=323333&r2=323334&view=diff ============================================================================== --- llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp Wed Jan 24 07:33:33 2018 @@ -142,6 +142,9 @@ PPCTargetLowering::PPCTargetLowering(con setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); + // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended. + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); + // PowerPC has an i16 but no i8 (or i1) SEXTLOAD. for (MVT VT : MVT::integer_valuetypes()) { setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); @@ -1154,6 +1157,8 @@ const char *PPCTargetLowering::getTarget case PPCISD::Hi: return "PPCISD::Hi"; case PPCISD::Lo: return "PPCISD::Lo"; case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; + case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8"; + case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16"; case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET"; case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; @@ -8834,6 +8839,42 @@ SDValue PPCTargetLowering::LowerBSWAP(SD return Op; } +// ATOMIC_CMP_SWAP for i8/i16 needs to zero-extend its input since it will be +// compared to a value that is atomically loaded (atomic loads zero-extend). +SDValue PPCTargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, + SelectionDAG &DAG) const { + assert(Op.getOpcode() == ISD::ATOMIC_CMP_SWAP && + "Expecting an atomic compare-and-swap here."); + SDLoc dl(Op); + auto *AtomicNode = cast<AtomicSDNode>(Op.getNode()); + EVT MemVT = AtomicNode->getMemoryVT(); + if (MemVT.getSizeInBits() >= 32) + return Op; + + SDValue CmpOp = Op.getOperand(2); + // If this is already correctly zero-extended, leave it alone. + auto HighBits = APInt::getHighBitsSet(32, 32 - MemVT.getSizeInBits()); + if (DAG.MaskedValueIsZero(CmpOp, HighBits)) + return Op; + + // Clear the high bits of the compare operand. + unsigned MaskVal = (1 << MemVT.getSizeInBits()) - 1; + SDValue NewCmpOp = + DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp, + DAG.getConstant(MaskVal, dl, MVT::i32)); + + // Replace the existing compare operand with the properly zero-extended one. + SmallVector<SDValue, 4> Ops; + for (int i = 0, e = AtomicNode->getNumOperands(); i < e; i++) + Ops.push_back(AtomicNode->getOperand(i)); + Ops[2] = NewCmpOp; + MachineMemOperand *MMO = AtomicNode->getMemOperand(); + SDVTList Tys = DAG.getVTList(MVT::i32, MVT::Other); + auto NodeTy = + (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16; + return DAG.getMemIntrinsicNode(NodeTy, dl, Tys, Ops, MemVT, MMO); +} + SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); @@ -9325,6 +9366,8 @@ SDValue PPCTargetLowering::LowerOperatio return LowerREM(Op, DAG); case ISD::BSWAP: return LowerBSWAP(Op, DAG); + case ISD::ATOMIC_CMP_SWAP: + return LowerATOMIC_CMP_SWAP(Op, DAG); } } Modified: llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.h?rev=323334&r1=323333&r2=323334&view=diff ============================================================================== --- llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.h (original) +++ llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.h Wed Jan 24 07:33:33 2018 @@ -430,6 +430,11 @@ namespace llvm { /// The 4xf32 load used for v4i1 constants. QVLFSb, + /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes + /// except they ensure that the compare input is zero-extended for + /// sub-word versions because the atomic loads zero-extend. + ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16, + /// GPRC = TOC_ENTRY GA, TOC /// Loads the entry for GA from the TOC, where the TOC base is given by /// the last operand. @@ -955,6 +960,7 @@ namespace llvm { SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; Modified: llvm/branches/release_60/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/PowerPC/PPCInstrInfo.td?rev=323334&r1=323333&r2=323334&view=diff ============================================================================== --- llvm/branches/release_60/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/branches/release_60/lib/Target/PowerPC/PPCInstrInfo.td Wed Jan 24 07:33:33 2018 @@ -257,6 +257,13 @@ def PPCvcmp_o : SDNode<"PPCISD::VCMP def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, [SDNPHasChain, SDNPOptInGlue]>; +// PPC-specific atomic operations. +def PPCatomicCmpSwap_8 : + SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; +def PPCatomicCmpSwap_16 : + SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, @@ -1710,6 +1717,11 @@ let usesCustomInserter = 1 in { } } +def : Pat<(PPCatomicCmpSwap_8 xoaddr:$ptr, i32:$old, i32:$new), + (ATOMIC_CMP_SWAP_I8 xoaddr:$ptr, i32:$old, i32:$new)>; +def : Pat<(PPCatomicCmpSwap_16 xoaddr:$ptr, i32:$old, i32:$new), + (ATOMIC_CMP_SWAP_I16 xoaddr:$ptr, i32:$old, i32:$new)>; + // Instructions to support atomic operations let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src), Modified: llvm/branches/release_60/test/CodeGen/AArch64/atomic-ops-lse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/AArch64/atomic-ops-lse.ll?rev=323334&r1=323333&r2=323334&view=diff ============================================================================== --- llvm/branches/release_60/test/CodeGen/AArch64/atomic-ops-lse.ll (original) +++ llvm/branches/release_60/test/CodeGen/AArch64/atomic-ops-lse.ll Wed Jan 24 07:33:33 2018 @@ -629,12 +629,27 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wa ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 +; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 +; CHECK-NEXT: casab w0, w1, [x[[ADDR]]] +; CHECK-NEXT: ret + + ret i8 %old +} + +define i1 @test_atomic_cmpxchg_i8_1(i8 %wanted, i8 %new) nounwind { +; CHECK-LABEL: test_atomic_cmpxchg_i8_1: + %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire + %success = extractvalue { i8, i1 } %pair, 1 -; CHECK: casab w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]] ; CHECK-NOT: dmb +; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 - ret i8 %old +; CHECK: casab w[[NEW:[0-9]+]], w1, [x[[ADDR]]] +; CHECK-NEXT: cmp w[[NEW]], w0, uxtb +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret + ret i1 %success } define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { @@ -644,12 +659,28 @@ define i16 @test_atomic_cmpxchg_i16(i16 ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 +; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 +; CHECK-NEXT: casah w0, w1, [x[[ADDR]]] +; CHECK-NEXT: ret + + ret i16 %old +} + +define i1 @test_atomic_cmpxchg_i16_1(i16 %wanted, i16 %new) nounwind { +; CHECK-LABEL: test_atomic_cmpxchg_i16_1: + %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new acquire acquire + %success = extractvalue { i16, i1 } %pair, 1 -; CHECK: casah w0, w1, [x[[ADDR]]] ; CHECK-NOT: dmb +; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 +; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 - ret i16 %old +; CHECK: casah w[[NEW:[0-9]+]], w1, [x[[ADDR]]] +; CHECK-NEXT: cmp w[[NEW]], w0, uxth +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret + + ret i1 %success } define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { Modified: llvm/branches/release_60/test/CodeGen/ARM/atomic-cmpxchg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/ARM/atomic-cmpxchg.ll?rev=323334&r1=323333&r2=323334&view=diff ============================================================================== --- llvm/branches/release_60/test/CodeGen/ARM/atomic-cmpxchg.ll (original) +++ llvm/branches/release_60/test/CodeGen/ARM/atomic-cmpxchg.ll Wed Jan 24 07:33:33 2018 @@ -49,9 +49,10 @@ entry: ; CHECK-THUMBV6: mov [[EXPECTED:r[0-9]+]], r1 ; CHECK-THUMBV6-NEXT: bl __sync_val_compare_and_swap_1 ; CHECK-THUMBV6-NEXT: mov [[RES:r[0-9]+]], r0 +; CHECK-THUMBV6-NEXT: uxtb [[EXPECTED_ZEXT:r[0-9]+]], [[EXPECTED]] ; CHECK-THUMBV6-NEXT: movs r0, #1 ; CHECK-THUMBV6-NEXT: movs [[ZERO:r[0-9]+]], #0 -; CHECK-THUMBV6-NEXT: cmp [[RES]], [[EXPECTED]] +; CHECK-THUMBV6-NEXT: cmp [[RES]], [[EXPECTED_ZEXT]] ; CHECK-THUMBV6-NEXT: beq [[END:.LBB[0-9_]+]] ; CHECK-THUMBV6-NEXT: mov r0, [[ZERO]] ; CHECK-THUMBV6-NEXT: [[END]]: Modified: llvm/branches/release_60/test/CodeGen/ARM/cmpxchg-O0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/ARM/cmpxchg-O0.ll?rev=323334&r1=323333&r2=323334&view=diff ============================================================================== --- llvm/branches/release_60/test/CodeGen/ARM/cmpxchg-O0.ll (original) +++ llvm/branches/release_60/test/CodeGen/ARM/cmpxchg-O0.ll Wed Jan 24 07:33:33 2018 @@ -17,7 +17,8 @@ define { i8, i1 } @test_cmpxchg_8(i8* %a ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 ; CHECK: bne [[RETRY]] ; CHECK: [[DONE]]: -; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED]] +; CHECK: uxtb [[DESIRED_ZEXT:r[0-9]+]], [[DESIRED]] +; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED_ZEXT]] ; CHECK: {{moveq|movweq}} {{r[0-9]+}}, #1 ; CHECK: dmb ish %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic @@ -36,7 +37,8 @@ define { i16, i1 } @test_cmpxchg_16(i16* ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 ; CHECK: bne [[RETRY]] ; CHECK: [[DONE]]: -; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED]] +; CHECK: uxth [[DESIRED_ZEXT:r[0-9]+]], [[DESIRED]] +; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED_ZEXT]] ; CHECK: {{moveq|movweq}} {{r[0-9]+}}, #1 ; CHECK: dmb ish %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic Copied: llvm/branches/release_60/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll (from r322372, llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll) URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll?p2=llvm/branches/release_60/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll&p1=llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll&r1=322372&r2=323334&rev=323334&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll (original) +++ llvm/branches/release_60/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll Wed Jan 24 07:33:33 2018 @@ -26,9 +26,7 @@ define signext i32 @main() { ; CHECK: .LBB0_3: # %L.entry ; CHECK: sthcx. 3, 0, 5 ; CHECK: .LBB0_4: # %L.entry -; Once D41798 lands, this should be the check: -; FIXME: cmplwi 3, 33059 -; CHECK: cmpwi 3, -32477 +; CHECK: cmplwi 3, 33059 ; CHECK: lwsync ; CHECK: lhz 3, 46(1) ; CHECK: cmplwi 3, 234 @@ -64,9 +62,7 @@ define signext i32 @main() { ; CHECK-P7: .LBB0_4: # %L.entry ; CHECK-P7: srw 3, 6, 3 ; CHECK-P7: lwsync -; Once D41798 lands, this should be the check: -; FIXME: cmplwi 3, 33059 -; CHECK-P7: cmpwi 3, -32477 +; CHECK-P7: cmplwi 3, 33059 ; CHECK-P7: lhz 3, 46(1) ; CHECK-P7: cmplwi 3, 234 L.entry: Modified: llvm/branches/release_60/test/CodeGen/PowerPC/atomics-regression.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/PowerPC/atomics-regression.ll?rev=323334&r1=323333&r2=323334&view=diff ============================================================================== --- llvm/branches/release_60/test/CodeGen/PowerPC/atomics-regression.ll (original) +++ llvm/branches/release_60/test/CodeGen/PowerPC/atomics-regression.ll Wed Jan 24 07:33:33 2018 @@ -404,6 +404,7 @@ define void @test39() { define void @test40(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test40: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: b .LBB40_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB40_1: @@ -423,6 +424,7 @@ define void @test40(i8* %ptr, i8 %cmp, i define void @test41(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test41: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: .LBB41_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 @@ -444,6 +446,7 @@ define void @test41(i8* %ptr, i8 %cmp, i define void @test42(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test42: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: .LBB42_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 @@ -465,6 +468,7 @@ define void @test42(i8* %ptr, i8 %cmp, i define void @test43(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test43: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB43_2 ; PPC64LE-NEXT: .p2align 5 @@ -485,6 +489,7 @@ define void @test43(i8* %ptr, i8 %cmp, i define void @test44(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test44: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB44_2 ; PPC64LE-NEXT: .p2align 5 @@ -505,6 +510,7 @@ define void @test44(i8* %ptr, i8 %cmp, i define void @test45(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test45: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB45_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -527,6 +533,7 @@ define void @test45(i8* %ptr, i8 %cmp, i define void @test46(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test46: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB46_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -549,6 +556,7 @@ define void @test46(i8* %ptr, i8 %cmp, i define void @test47(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test47: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB47_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -571,6 +579,7 @@ define void @test47(i8* %ptr, i8 %cmp, i define void @test48(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test48: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB48_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -593,6 +602,7 @@ define void @test48(i8* %ptr, i8 %cmp, i define void @test49(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test49: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB49_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -615,6 +625,7 @@ define void @test49(i8* %ptr, i8 %cmp, i define void @test50(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test50: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: b .LBB50_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB50_1: @@ -634,6 +645,7 @@ define void @test50(i16* %ptr, i16 %cmp, define void @test51(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test51: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: .LBB51_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 @@ -655,6 +667,7 @@ define void @test51(i16* %ptr, i16 %cmp, define void @test52(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test52: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: .LBB52_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 @@ -676,6 +689,7 @@ define void @test52(i16* %ptr, i16 %cmp, define void @test53(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test53: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB53_2 ; PPC64LE-NEXT: .p2align 5 @@ -696,6 +710,7 @@ define void @test53(i16* %ptr, i16 %cmp, define void @test54(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test54: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB54_2 ; PPC64LE-NEXT: .p2align 5 @@ -716,6 +731,7 @@ define void @test54(i16* %ptr, i16 %cmp, define void @test55(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test55: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB55_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -738,6 +754,7 @@ define void @test55(i16* %ptr, i16 %cmp, define void @test56(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test56: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB56_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -760,6 +777,7 @@ define void @test56(i16* %ptr, i16 %cmp, define void @test57(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test57: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB57_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -782,6 +800,7 @@ define void @test57(i16* %ptr, i16 %cmp, define void @test58(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test58: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB58_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -804,6 +823,7 @@ define void @test58(i16* %ptr, i16 %cmp, define void @test59(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test59: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB59_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -1248,6 +1268,7 @@ define void @test79(i64* %ptr, i64 %cmp, define void @test80(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test80: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: b .LBB80_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB80_1: @@ -1267,6 +1288,7 @@ define void @test80(i8* %ptr, i8 %cmp, i define void @test81(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test81: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: .LBB81_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 @@ -1288,6 +1310,7 @@ define void @test81(i8* %ptr, i8 %cmp, i define void @test82(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test82: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: .LBB82_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 @@ -1309,6 +1332,7 @@ define void @test82(i8* %ptr, i8 %cmp, i define void @test83(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test83: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB83_2 ; PPC64LE-NEXT: .p2align 5 @@ -1329,6 +1353,7 @@ define void @test83(i8* %ptr, i8 %cmp, i define void @test84(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test84: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB84_2 ; PPC64LE-NEXT: .p2align 5 @@ -1349,6 +1374,7 @@ define void @test84(i8* %ptr, i8 %cmp, i define void @test85(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test85: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB85_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -1371,6 +1397,7 @@ define void @test85(i8* %ptr, i8 %cmp, i define void @test86(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test86: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB86_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -1393,6 +1420,7 @@ define void @test86(i8* %ptr, i8 %cmp, i define void @test87(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test87: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB87_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -1415,6 +1443,7 @@ define void @test87(i8* %ptr, i8 %cmp, i define void @test88(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test88: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB88_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -1437,6 +1466,7 @@ define void @test88(i8* %ptr, i8 %cmp, i define void @test89(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test89: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB89_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 @@ -1459,6 +1489,7 @@ define void @test89(i8* %ptr, i8 %cmp, i define void @test90(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test90: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: b .LBB90_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB90_1: @@ -1478,6 +1509,7 @@ define void @test90(i16* %ptr, i16 %cmp, define void @test91(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test91: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: .LBB91_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 @@ -1499,6 +1531,7 @@ define void @test91(i16* %ptr, i16 %cmp, define void @test92(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test92: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: .LBB92_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 @@ -1520,6 +1553,7 @@ define void @test92(i16* %ptr, i16 %cmp, define void @test93(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test93: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB93_2 ; PPC64LE-NEXT: .p2align 5 @@ -1540,6 +1574,7 @@ define void @test93(i16* %ptr, i16 %cmp, define void @test94(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test94: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB94_2 ; PPC64LE-NEXT: .p2align 5 @@ -1560,6 +1595,7 @@ define void @test94(i16* %ptr, i16 %cmp, define void @test95(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test95: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB95_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -1582,6 +1618,7 @@ define void @test95(i16* %ptr, i16 %cmp, define void @test96(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test96: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB96_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -1604,6 +1641,7 @@ define void @test96(i16* %ptr, i16 %cmp, define void @test97(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test97: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB97_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -1626,6 +1664,7 @@ define void @test97(i16* %ptr, i16 %cmp, define void @test98(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test98: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB98_1: ; PPC64LE-NEXT: lharx 6, 0, 3 @@ -1648,6 +1687,7 @@ define void @test98(i16* %ptr, i16 %cmp, define void @test99(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test99: ; PPC64LE: # %bb.0: +; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB99_1: ; PPC64LE-NEXT: lharx 6, 0, 3 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
