Dan Malek writes: > An instuction TLB miss will load the TLB with a PTE that indicates it isn't > valid. A subsequent TLB instruction fault to load the page will cause a
If the PTE isn't valid (i.e. the _PAGE_PRESENT bit is 0) we don't put it into the TLB. If we did it would be ignored by the hardware and we would get another TLB miss straight away. I believe that on 8xx you actually have two valid bits in each TLB entry, so you can have a TLB entry that is "valid" but describes a non-present page. That isn't the case on 4xx. Paul. ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
