Matthew Trescott writes:
> Hi Dave,
>
> > Some info about my board:
> >
> > I'm using a RTL8201F phy on the PG pins in RMII mode and want to use
> > the EPHY-25M clock output on PG11 to drive the phy so no external
> > crystal is needed.
> >
> >
> > Kernel: https://github.com/smaeul/linux.git at
> b466df90d48fb7ef03f331e0c73c8012ac03a12e
>
> Do you have a scope to check this net on the board? As far as I know you need
> a patch that's not in mainline or smaeul's kernel:
>
> https://oftc.irclog.whitequark.org/linux-sunxi/2023-02-14
Added that patch and moved my <&ccu CLK_EMAC_25M> into the mdio/phy DT
section.
Manually setting EMAC_25M_CLK_REG does work and produces a nice 25Mhz
sine wave clock output on the pin, however the driver isn't doing this
(even with that patch). The driver does release phy reset during
init, but not enable the 25mhz clock output.
If I manually (outside of the driver) release the phy reset GPIO and
enable the 25mhz output, the phy comes online and starts generating a
50mhz clock back towards the MAC on the RMII-TXCK pin.
I verified clocks going in both directions with a scope and once the
TXCK clock makes it back to the EMAC from the PHY it looks like it
will exit soft-reset.
So at this point, getting the ephy-25mhz enabled by mac and/or mdio
drivers should fix things.
I placed these in both the mdiobus and phy clauses of the DTS but it's
not getting picked up:
clocks = <&ccu CLK_EMAC_25M>;
clock-names = "ephy25m";
>
> > Has anyone succesfully got the T113/D1 EMAC to work, especially in RMII
> mode?
>
> There are a few other reports of actual boards using RMII + 25MHz clock
> output, probably only using the BSP kernel though:
>
> https://oftc.irclog.whitequark.org/linux-sunxi/2023-07-29
> https://oftc.irclog.whitequark.org/linux-sunxi/2022-06-07#30990410
>
> I would be interested in hearing what you find out, since I'm looking to make
> my own Lichee RV (D1) carrier board and I also like to be a cheapskate when
> it
> comes to hardware. :)
>
> Kind regards,
> Matt
>
>
--
Dave
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