Ensure the PWM clock is enabled prior to retrieving its rate, as is already being done in sun4i_pwm_apply.
Signed-off-by: Roman Beranek <[email protected]> --- drivers/pwm/pwm-sun4i.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index e01becd102c0..3721b9894cf6 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -117,8 +117,15 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, u64 clk_rate, tmp; u32 val; unsigned int prescaler; + int ret; + ret = clk_prepare_enable(sun4i_pwm->clk); + if (ret) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return; + } clk_rate = clk_get_rate(sun4i_pwm->clk); + clk_disable_unprepare(sun4i_pwm->clk); val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); -- 2.31.1 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210531044608.1006024-2-roman.beranek%40prusa3d.com.
