As Emil Lenngren has previously shown [1], actually only 1-2 cycles of the prescaler-divided clock are necessary to pass before the PWM turns off, not a full period.
To avoid having the PWM re-enabled from another thread while asleep, ctrl_lock spinlock was converted to a mutex so that it can be released only after the clock gate has finally been turned on. [1] https://linux-sunxi.org/PWM_Controller_Register_Guide Roman Beranek (6): pwm: sun4i: enable clk prior to getting its rate pwm: sun4i: disable EN bit prior to the delay pwm: sun4i: replace spinlock with a mutex pwm: sun4i: simplify calculation of the delay time pwm: sun4i: shorten the delay to 2 cycles pwm: sun4i: don't delay if the PWM is already off drivers/pwm/pwm-sun4i.c | 56 +++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 30 deletions(-) -- 2.31.1 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210531044608.1006024-1-roman.beranek%40prusa3d.com.
