Hello Uwe, Correct, the output may stay in an active state. I only discovered this bug as I investigated a report of unreliable screen timeout. The period we use the PWM with is 50 us.
The PWMx_RDY bit stays 0 well after the last period ends, so if the bit has any function at all, this one is certainly not it. Cheers, Roman On Wed, Apr 28, 2021 at 8:14 AM Uwe Kleine-König < [email protected]> wrote: > Hello Roman, > > On Wed, Apr 28, 2021 at 02:19:46AM +0200, Roman Beranek wrote: > > More often than not, a PWM period may span nowhere near as far > > as 1 jiffy, yet it still must be waited upon before the channel > > is disabled. > > I wonder what happens if you don't wait long enough. Is this a > theoretical issue, or do you see an (occasional?) breakage that is fixed > by this patch? > > I guess the problem is that if you disable too early the output freezes > and that might be in a state where the output is still active? Would > polling the PWMx_RDY bit in the control register help here? > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | https://www.pengutronix.de/ | > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAL8eAtopkMVmt8XDbzLRsJ_JgGNwZ-FgdNPOWkh-yboTqceUyw%40mail.gmail.com.
