Hi!
Just some nit-picking... (not worth blocking apply for this, can
easily go through trivial tree later.)
> create mode 100644 Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
> b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
> new file mode 100644
> index 0000000..f36b7ee
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
> @@ -0,0 +1,60 @@
> +* Altera SOCFPGA specific extensions to the Synopsis Designware Mobile
> + Storage Host Controller
> +
> +Required Properties:
> +
> +* compatible: should be
> + - "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA
> + specific extensions.
> +
> +* altr,dw-mshc-ciu-div: Specifies the divider value for the card interface
> + unit (ciu) clock. The value should be (n+1). For Altera's SOCFPGA, the
> divider
> + value is fixed at 3, which mean parent_clock/4.
"which means".
> +* altr,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
> + in transmit mode and CIU clock phase shift value in receive mode for single
> + data rate mode operation. Refer notes below for the order of the cells and
> the
"refer to".
> +Example:
> +
> + The MSHC controller node can be split into two portions, SoC specific and
> + board specific portions as listed below.
", as listed".
Thanks,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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