From: RichardZhu <[email protected]>
On i.MX6, if the TC interrupt bit is set but the DMA interrupt bit is cleared,
read the status register again in case the DMA interrupt will come in next
time cycle.
Note: This is a workaround for i.MX6 version 1.0 silicon. It's fixed in
hardware in
version 1.1 silicon.
Signed-off-by: Tony Lin <[email protected]>
Signed-off-by: RichardZhu <[email protected]>
Signed-off-by: Philipp Ahmann <[email protected]>
---
drivers/mmc/host/sdhci-esdhc-imx.c | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index af2f581..a13e75b 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -180,6 +180,19 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
}
if (unlikely(reg == SDHCI_INT_STATUS)) {
+ if (is_imx6q_usdhc(imx_data)) {
+ /*
+ * on mx6q, there is low possibility that
+ * DATA END interrupt comes ealier than DMA
+ * END interrupt which is conflict with standard
+ * host controller spec. In this case, read the
+ * status register again will workaround this issue.
+ */
+ if ((val & SDHCI_INT_DATA_END) && \
+ !(val & SDHCI_INT_DMA_END))
+ val = readl(host->ioaddr + reg);
+ }
+
if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
val |= SDHCI_INT_ADMA_ERROR;
--
1.7.0.4
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