On Thu, 09 Jul 2026 23:39:41 -0700, Ananthu C V wrote:
> The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls
> USB Type-C, battery charging and various other functions on Qualcomm SoCs.
> This series add the nodes required to enable SoCCP on Glymur/Mahua SoCs.
>
> It also introduces the needs_tzmem flag which would cover for certain edge
> cases by serving as an alternate trigger to the PAS helpers to ensure that
> SHM bridge is established on SoCs running non-Gunyah based Hypervisors. This
> change is required for SSR to work on SoCCP on Glymur.
>
> [...]
Applied, thanks!
[3/4] arm64: dts: qcom: fix SoCCP memory mappings for Glymur
commit: 61e5b39e96aadeafa884ab96c1477b781dccf145
[4/4] arm64: dts: qcom: add SoCCP DT node for Glymur
commit: fe76d6b32eb2d3193c65c834693fa4f58b558080
Best regards,
--
Bjorn Andersson <[email protected]>
