Use the generic TIF bits defined in <asm-generic/thread_info_tif.h> for standard thread flags (TIF_SIGPENDING, TIF_NEED_RESCHED, TIF_NOTIFY_RESUME, TIF_RESTORE_SIGMASK, TIF_SINGLESTEP, etc.) instead of defining them locally.
Arm64-specific bits (TIF_FOREIGN_FPSTATE, TIF_MTE_ASYNC_FAULT, TIF_SVE, TIF_SSBD, etc.) are renumbered to start at bit 16 to avoid conflicts. This enables RSEQ optimizations which require CONFIG_HAVE_GENERIC_TIF_BITS combined with the generic entry infrastructure (already used by arm64). Signed-off-by: Jinjie Ruan <[email protected]> --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/thread_info.h | 62 ++++++++++++--------------- arch/s390/include/asm/thread_info.h | 7 ++- arch/x86/include/asm/thread_info.h | 6 +-- include/asm-generic/thread_info_tif.h | 5 +++ 5 files changed, 38 insertions(+), 43 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 96fef01598be..33cf901fb1a0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -224,6 +224,7 @@ config ARM64 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI select HAVE_BUILDTIME_MCOUNT_SORT select HAVE_EFFICIENT_UNALIGNED_ACCESS + select HAVE_GENERIC_TIF_BITS select HAVE_GUP_FAST select HAVE_FTRACE_GRAPH_FUNC select HAVE_FUNCTION_TRACER diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h index f89a15dc6ad5..be1a0651cfe2 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -58,42 +58,34 @@ void arch_setup_new_exec(void); #endif -#define TIF_SIGPENDING 0 /* signal pending */ -#define TIF_NEED_RESCHED 1 /* rescheduling necessary */ -#define TIF_NEED_RESCHED_LAZY 2 /* Lazy rescheduling needed */ -#define TIF_NOTIFY_RESUME 3 /* callback before returning to user */ -#define TIF_FOREIGN_FPSTATE 4 /* CPU's FP state is not current's */ -#define TIF_UPROBE 5 /* uprobe breakpoint or singlestep */ -#define TIF_MTE_ASYNC_FAULT 6 /* MTE Asynchronous Tag Check Fault */ -#define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */ -#define TIF_PATCH_PENDING 13 /* pending live patching update */ -#define TIF_MEMDIE 18 /* is terminating due to OOM killer */ -#define TIF_FREEZE 19 -#define TIF_RESTORE_SIGMASK 20 -#define TIF_SINGLESTEP 21 -#define TIF_32BIT 22 /* 32bit process */ -#define TIF_SVE 23 /* Scalable Vector Extension in use */ -#define TIF_SVE_VL_INHERIT 24 /* Inherit SVE vl_onexec across exec */ -#define TIF_SSBD 25 /* Wants SSB mitigation */ -#define TIF_TAGGED_ADDR 26 /* Allow tagged user addresses */ -#define TIF_SME 27 /* SME in use */ -#define TIF_SME_VL_INHERIT 28 /* Inherit SME vl_onexec across exec */ -#define TIF_KERNEL_FPSTATE 29 /* Task is in a kernel mode FPSIMD section */ -#define TIF_TSC_SIGSEGV 30 /* SIGSEGV on counter-timer access */ -#define TIF_LAZY_MMU_PENDING 31 /* Ops pending for lazy mmu mode exit */ +/* + * Tell the generic TIF infrastructure which bits arm64 supports + */ +#define HAVE_TIF_NEED_RESCHED_LAZY +#define HAVE_TIF_RESTORE_SIGMASK +#define HAVE_TIF_SINGLESTEP + +#include <asm-generic/thread_info_tif.h> + +#define TIF_FOREIGN_FPSTATE 16 /* CPU's FP state is not current's */ +#define TIF_MTE_ASYNC_FAULT 17 /* MTE Asynchronous Tag Check Fault */ +#define TIF_FREEZE 18 +#define TIF_32BIT 19 /* 32bit process */ +#define TIF_SVE 20 /* Scalable Vector Extension in use */ +#define TIF_SVE_VL_INHERIT 21 /* Inherit SVE vl_onexec across exec */ +#define TIF_SSBD 22 /* Wants SSB mitigation */ +#define TIF_TAGGED_ADDR 23 /* Allow tagged user addresses */ +#define TIF_SME 24 /* SME in use */ +#define TIF_SME_VL_INHERIT 25 /* Inherit SME vl_onexec across exec */ +#define TIF_KERNEL_FPSTATE 26 /* Task is in a kernel mode FPSIMD section */ +#define TIF_TSC_SIGSEGV 27 /* SIGSEGV on counter-timer access */ +#define TIF_LAZY_MMU_PENDING 28 /* Ops pending for lazy mmu mode exit */ -#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) -#define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE) -#define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING) -#define _TIF_UPROBE (1 << TIF_UPROBE) -#define _TIF_32BIT (1 << TIF_32BIT) -#define _TIF_SVE (1 << TIF_SVE) -#define _TIF_MTE_ASYNC_FAULT (1 << TIF_MTE_ASYNC_FAULT) -#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) -#define _TIF_TSC_SIGSEGV (1 << TIF_TSC_SIGSEGV) +#define _TIF_FOREIGN_FPSTATE BIT(TIF_FOREIGN_FPSTATE) +#define _TIF_32BIT BIT(TIF_32BIT) +#define _TIF_SVE BIT(TIF_SVE) +#define _TIF_MTE_ASYNC_FAULT BIT(TIF_MTE_ASYNC_FAULT) +#define _TIF_TSC_SIGSEGV BIT(TIF_TSC_SIGSEGV) #ifdef CONFIG_SHADOW_CALL_STACK #define INIT_SCS \ diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h index 1bcd42614e41..95be5258a422 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -61,6 +61,7 @@ void arch_setup_new_exec(void); */ #define HAVE_TIF_NEED_RESCHED_LAZY #define HAVE_TIF_RESTORE_SIGMASK +#define HAVE_TIF_SINGLESTEP #include <asm-generic/thread_info_tif.h> @@ -69,15 +70,13 @@ void arch_setup_new_exec(void); #define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */ #define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated BP */ #define TIF_PER_TRAP 19 /* Need to handle PER trap on exit to usermode */ -#define TIF_SINGLESTEP 21 /* This task is single stepped */ -#define TIF_BLOCK_STEP 22 /* This task is block stepped */ -#define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single stepped */ +#define TIF_BLOCK_STEP 20 /* This task is block stepped */ +#define TIF_UPROBE_SINGLESTEP 21 /* This task is uprobe single stepped */ #define _TIF_ASCE_PRIMARY BIT(TIF_ASCE_PRIMARY) #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE) #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST) #define _TIF_PER_TRAP BIT(TIF_PER_TRAP) -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP) #define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP) diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 0067684afb5b..f59072ba1473 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -98,9 +98,8 @@ struct thread_info { #define TIF_IO_BITMAP 22 /* uses I/O bitmap */ #define TIF_SPEC_FORCE_UPDATE 23 /* Force speculation MSR update in context switch */ #define TIF_FORCED_TF 24 /* true if TF in eflags artificially */ -#define TIF_SINGLESTEP 25 /* reenable singlestep on user return*/ -#define TIF_BLOCKSTEP 26 /* set when we want DEBUGCTLMSR_BTF */ -#define TIF_ADDR32 27 /* 32-bit address space on 64 bits */ +#define TIF_BLOCKSTEP 25 /* set when we want DEBUGCTLMSR_BTF */ +#define TIF_ADDR32 26 /* 32-bit address space on 64 bits */ #define _TIF_SSBD BIT(TIF_SSBD) #define _TIF_SPEC_IB BIT(TIF_SPEC_IB) @@ -112,7 +111,6 @@ struct thread_info { #define _TIF_SPEC_FORCE_UPDATE BIT(TIF_SPEC_FORCE_UPDATE) #define _TIF_FORCED_TF BIT(TIF_FORCED_TF) #define _TIF_BLOCKSTEP BIT(TIF_BLOCKSTEP) -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_ADDR32 BIT(TIF_ADDR32) /* flags to check in __switch_to() */ diff --git a/include/asm-generic/thread_info_tif.h b/include/asm-generic/thread_info_tif.h index da1610a78f92..b277fe06aee3 100644 --- a/include/asm-generic/thread_info_tif.h +++ b/include/asm-generic/thread_info_tif.h @@ -48,4 +48,9 @@ #define TIF_RSEQ 11 // Run RSEQ fast path #define _TIF_RSEQ BIT(TIF_RSEQ) +#ifdef HAVE_TIF_SINGLESTEP +#define TIF_SINGLESTEP 12 /* reenable singlestep on user return*/ +#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) +#endif + #endif /* _ASM_GENERIC_THREAD_INFO_TIF_H_ */ -- 2.34.1
