On 4/6/25 3:52 PM, Luca Weiss wrote:
> From: Felix Kaechele <[email protected]>
>
> Add the node and pinctrl for uart_5 found on the MSM8953 SoC.
>
> Signed-off-by: Felix Kaechele <[email protected]>
> [luca: Prepare patch for upstream submission]
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/msm8953.dtsi | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi
> b/arch/arm64/boot/dts/qcom/msm8953.dtsi
> index
> af4c341e2533ef2cca593e0dc97003334d3fd6b7..3d6ab83cbce4696a8eb54b16fdb429e191f44637
> 100644
> --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
> @@ -767,6 +767,20 @@ spi_6_sleep: spi-6-sleep-state {
> bias-disable;
> };
>
> + uart_5_default: uart-5-default-state {
> + pins = "gpio16", "gpio17", "gpio18", "gpio19";
> + function = "blsp_uart5";
> + drive-strength = <16>;
This guy's strongly biased! But it looks like that's on purpose for
these older SoCs..
> + bias-disable;
> + };
> +
> + uart_5_sleep: uart-5-sleep-state {
> + pins = "gpio16", "gpio17", "gpio18", "gpio19";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> wcnss_pin_a: wcnss-active-state {
>
> wcss-wlan2-pins {
> @@ -1592,6 +1606,24 @@ blsp2_dma: dma-controller@7ac4000 {
> qcom,controlled-remotely;
> };
>
> + uart_5: serial@7aef000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x07aef000 0x200>;
> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
> + <&gcc GCC_BLSP2_AHB_CLK>;
> + clock-names = "core",
> + "iface";
> + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
> + dma-names = "tx", "rx";
Matches what the computer says
It's more usual to send these together with a user, but I don't mind
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
