On Wed, Jul 31, 2019 at 6:58 PM Atish Patra <[email protected]> wrote: > > Since the RISC-V specification states that ISA description strings are > case-insensitive, there's no functional difference between mixed-case, > upper-case, and lower-case ISA strings. Thus, to simplify parsing, > specify that the letters present in "riscv,isa" must be all lowercase. > > Suggested-by: Paul Walmsley <[email protected]> > Signed-off-by: Atish Patra <[email protected]> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml > b/Documentation/devicetree/bindings/riscv/cpus.yaml > index c899111aa5e3..4f0acb00185a 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -46,10 +46,12 @@ properties: > - rv64imafdc > description: > Identifies the specific RISC-V instruction set architecture > - supported by the hart. These are documented in the RISC-V > + supported by the hart. These are documented in the RISC-V > User-Level ISA document, available from > https://riscv.org/specifications/ > > + Letters in the riscv,isa string must be all lowercase. > +
The schemas are case sensitive this looks pretty pointless without the context of the commit msg. Can you prefix with 'While the specification is case insensitive, " For some background, FDT generally always has been case sensitive too (dtc won't merge/override nodes/properties with differing case). It's really only some older true OF systems that were case insensitive. The kernel had a mixture of case sensitive and insensitive comparisons somewhat depending on the arch and whether of_prop_cmp/of_node_cmp or str*cmp functions were used. There's been a lot of clean-up and now most comparisons are case sensitive with only Sparc having some deviation. Rob
