Since the RISC-V specification states that ISA description strings are case-insensitive, there's no functional difference between mixed-case, upper-case, and lower-case ISA strings. Thus, to simplify parsing, specify that the letters present in "riscv,isa" must be all lowercase.
Suggested-by: Paul Walmsley <[email protected]> Signed-off-by: Atish Patra <[email protected]> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c899111aa5e3..4f0acb00185a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -46,10 +46,12 @@ properties: - rv64imafdc description: Identifies the specific RISC-V instruction set architecture - supported by the hart. These are documented in the RISC-V + supported by the hart. These are documented in the RISC-V User-Level ISA document, available from https://riscv.org/specifications/ + Letters in the riscv,isa string must be all lowercase. + timebase-frequency: type: integer minimum: 1 -- 2.21.0
