On Mon, Apr 08, 2019 at 04:49:03PM +0100, Marc Zyngier wrote: > Only arch_timer_read_counter will guarantee that workarounds are > applied. So let's use this one instead of arch_counter_get_cntvct. > > Signed-off-by: Marc Zyngier <[email protected]>
Acked-by: Mark Rutland <[email protected]> Mark. > --- > arch/arm64/kernel/traps.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index 8ad119c3f665..6190a60388cf 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -493,7 +493,7 @@ static void cntvct_read_handler(unsigned int esr, struct > pt_regs *regs) > { > int rt = ESR_ELx_SYS64_ISS_RT(esr); > > - pt_regs_write_reg(regs, rt, arch_counter_get_cntvct()); > + pt_regs_write_reg(regs, rt, arch_timer_read_counter()); > arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); > } > > @@ -665,7 +665,7 @@ static void compat_cntvct_read_handler(unsigned int esr, > struct pt_regs *regs) > { > int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> > ESR_ELx_CP15_64_ISS_RT_SHIFT; > int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> > ESR_ELx_CP15_64_ISS_RT2_SHIFT; > - u64 val = arch_counter_get_cntvct(); > + u64 val = arch_timer_read_counter(); > > pt_regs_write_reg(regs, rt, lower_32_bits(val)); > pt_regs_write_reg(regs, rt2, upper_32_bits(val)); > -- > 2.20.1 >
