On Fri, 2019-03-22 at 16:49 +0000, Abel Vesa wrote: > Add generic i.MX8 SoC driver along with the i.MX8MQ SoC specific code. > For now, only i.MX8MQ revision B1 is supported. For any other, i.MX8MQ > revision it will print 'unknown'.
> +#define REV_B1 0x21 > + > +#define IMX8MQ_SW_INFO_B1 0x40 > +#define IMX8MQ_SW_MAGIC_B1 0xff0055aa > + > + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");+ > + ocotp_base = of_iomap(np, 0); > + > + magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1); > + if (magic == IMX8MQ_SW_MAGIC_B1) > + rev = REV_B1; This is based on ATF code in vendor tree, but shouldn't we have some sort of explanation for this "magic"? Looking at the OCOTP driver reg 0x40 is IMX_OCOTP_ADDR_DATA2 and it's used as part of fuse writes. According to the driver code 8mq is compatible with 7d and this write path is enabled for imx8mq-ocotp. Looking at the OCOTP manual reg 0x40 is OCOTP_HW_OCOTP_READ_FUSE_DATA and it's meant to be used together with IMX_OCOTP_ADDR_CTRL to read info. Maybe my manual (rev0 2018-01) is incorrect? Looking at the manual this will return the value of the fuse last requested via IMX_OCOTP_ADDR_CTRL but no such request is made in this driver. So reading from OCOTP 0x40 might return an unrelated value?! The manual does document that fuse 0x440[3:0] is a "silicon revision number"; maybe we should read that? -- Regards, Leonard
