On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne <[email protected]> wrote: > From: Stefan Kristiansson <[email protected]> > > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as > described in the Multi-core support section of the OpenRISC 1.2 > architecture specification: > > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf > > Each OpenRISC core contains a full interrupt controller which is used in > the SMP architecture for interrupt balancing. This IPI device, the > ompic, is the only external device required for enabling SMP on > OpenRISC. > > Pending ops are stored in a memory bit mask which can allow multiple > pending operations to be set and serviced at a time. This is mostly > borrowed from the alpha IPI implementation. > > Cc: Marc Zyngier <[email protected]> > Acked-by: Rob Herring <[email protected]> > Signed-off-by: Stefan Kristiansson <[email protected]> > [[email protected]: converted ops to bitmask, wrote commit message] > Signed-off-by: Stafford Horne <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]> Side question: what is your merge strategy for this? I can take it through the irqchip tree as it is standalone, but I'm open to other suggestions. Thanks, M. -- Jazz is not dead. It just smells funny.
