This patch adds the detailed corrleation between sub-blocks and VDD_INT power line for Exynos5433. VDD_INT provided the power source to INT (Internal) block.
Cc: MyungJoo Ham <[email protected]> Cc: Kyungmin Park <[email protected]> Cc: Rob Herring <[email protected]> Cc: [email protected] Signed-off-by: Chanwoo Choi <[email protected]> --- Documentation/devicetree/bindings/devfreq/exynos-bus.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index d3ec8e676b6b..d6107770face 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -123,6 +123,21 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC: |--- FSYS |--- FSYS2 +- In case of Exynos5433, there is VDD_INT power line as following: + VDD_INT |--- G2D_400 (parent device) + |--- G2D_266 + |--- GSCL + |--- JPEG + |--- HEVC + |--- MFC + |--- MSCL + |--- NoC0 + |--- NoC1 + |--- NoC2 + |--- PERIS (Fixed clock rate) + |--- PERIC (Fixed clock rate) + |--- FSYS (Fixed clock rate) + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to -- 1.9.1
