Hi,
> if (sdd->port_conf->clk_from_cmu) {
> - /* Configure Clock */
> - /* There is half-multiplier before the SPI */
> clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
sorry, I will re-send it because I should not remove the comments
above.... in the future someone might wonder why it's multiplied
by 2.
That's called auto review and auto-nack :)
Andi
> - /* Enable Clock */
> - clk_prepare_enable(sdd->src_clk);
> } else {
> /* Configure Clock */
> val = readl(regs + S3C64XX_SPI_CLK_CFG);
> --
> 2.8.1
>
