On Mon, Oct 26, 2015 at 09:22:50PM +0100, Borislav Petkov wrote:
> And btw, those Intel QoS single bit defines and the XSAVE stuff there
> should move to that function too - that's a pure waste having them in
> the cap_flags array. I'll fix that.

I.e., something like that (I'm jetlagged and I can't sleep, bah :-\).

So this one builds but no further guarantees. It looks straightforward
though.

Not-yet-signed-off-by: Borislav Petkov <[email protected]>

---
diff --git a/arch/x86/include/asm/cpufeature.h 
b/arch/x86/include/asm/cpufeature.h
index 9727b3b48bd1..ea109b58a864 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
 #include <asm/disabled-features.h>
 #endif
 
-#define NCAPINTS       13      /* N 32-bit words worth of info */
+#define NCAPINTS       10      /* N 32-bit words worth of info */
 #define NBUGINTS       1       /* N 32-bit bug flags */
 
 /*
@@ -198,6 +198,15 @@
 #define X86_FEATURE_HWP_EPP    ( 7*32+13) /* Intel HWP_EPP */
 #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */
 #define X86_FEATURE_INTEL_PT   ( 7*32+15) /* Intel Processor Trace */
+/* Extended state features, CPUID level 0x0000000d:1 (eax) */
+#define X86_FEATURE_XSAVEOPT   (7*32+ 16) /* XSAVEOPT */
+#define X86_FEATURE_XSAVEC     (7*32+ 17) /* XSAVEC */
+#define X86_FEATURE_XGETBV1    (7*32+ 18) /* XGETBV with ECX = 1 */
+#define X86_FEATURE_XSAVES     (7*32+ 19) /* XSAVES/XRSTORS */
+/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx) */
+#define X86_FEATURE_CQM_LLC    (7*32+ 20) /* LLC QoS if 1 */
+/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx) */
+#define X86_FEATURE_CQM_OCCUP_LLC (7*32+ 21) /* LLC occupancy monitoring if 1 
*/
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
@@ -243,18 +252,6 @@
 #define X86_FEATURE_AVX512CD   ( 9*32+28) /* AVX-512 Conflict Detection */
 #define X86_FEATURE_SHA_NI     ( 9*32+29) /* SHA1/SHA256 Instruction 
Extensions */
 
-/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
-#define X86_FEATURE_XSAVEOPT   (10*32+ 0) /* XSAVEOPT */
-#define X86_FEATURE_XSAVEC     (10*32+ 1) /* XSAVEC */
-#define X86_FEATURE_XGETBV1    (10*32+ 2) /* XGETBV with ECX = 1 */
-#define X86_FEATURE_XSAVES     (10*32+ 3) /* XSAVES/XRSTORS */
-
-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
-#define X86_FEATURE_CQM_LLC    (11*32+ 1) /* LLC QoS if 1 */
-
-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
-#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 
*/
-
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index de22ea7ff82f..eb2a7e0636a3 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -621,29 +621,18 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
                c->x86_capability[9] = ebx;
        }
 
-       /* Extended state features: level 0x0000000d */
-       if (c->cpuid_level >= 0x0000000d) {
-               u32 eax, ebx, ecx, edx;
-
-               cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
-
-               c->x86_capability[10] = eax;
-       }
-
        /* Additional Intel-defined flags: level 0x0000000F */
        if (c->cpuid_level >= 0x0000000F) {
                u32 eax, ebx, ecx, edx;
 
                /* QoS sub-leaf, EAX=0Fh, ECX=0 */
                cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
-               c->x86_capability[11] = edx;
                if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
                        /* will be overridden if occupancy monitoring exists */
                        c->x86_cache_max_rmid = ebx;
 
                        /* QoS sub-leaf, EAX=0Fh, ECX=1 */
                        cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
-                       c->x86_capability[12] = edx;
                        if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) {
                                c->x86_cache_max_rmid = ecx;
                                c->x86_cache_occ_scale = ebx;
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 608fb26c7254..d9cf6ec2bdad 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -41,9 +41,15 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
                { X86_FEATURE_HWP_ACT_WINDOW,   CR_EAX, 9, 0x00000006, 0 },
                { X86_FEATURE_HWP_EPP,          CR_EAX,10, 0x00000006, 0 },
                { X86_FEATURE_HWP_PKG_REQ,      CR_EAX,11, 0x00000006, 0 },
-               { X86_FEATURE_INTEL_PT,         CR_EBX,25, 0x00000007, 0 },
                { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006, 0 },
                { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006, 0 },
+               { X86_FEATURE_INTEL_PT,         CR_EBX,25, 0x00000007, 0 },
+               { X86_FEATURE_XSAVEOPT,         CR_EAX, 0, 0x0000000d, 1 },
+               { X86_FEATURE_XSAVEC,           CR_EAX, 1, 0x0000000d, 1 },
+               { X86_FEATURE_XGETBV1,          CR_EAX, 2, 0x0000000d, 1 },
+               { X86_FEATURE_XSAVES,           CR_EAX, 3, 0x0000000d, 1 },
+               { X86_FEATURE_CQM_LLC,          CR_EDX, 1, 0x0000000f, 0 },
+               { X86_FEATURE_CQM_OCCUP_LLC,    CR_EDX, 0, 0x0000000f, 1 },
                { X86_FEATURE_HW_PSTATE,        CR_EDX, 7, 0x80000007, 0 },
                { X86_FEATURE_CPB,              CR_EDX, 9, 0x80000007, 0 },
                { X86_FEATURE_PROC_FEEDBACK,    CR_EDX,11, 0x80000007, 0 },

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
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