On 9 December 2010 21:51, Ramana Radhakrishnan <ramra...@arm.com> wrote: > On 9 Dec 2010, at 15:19, "Julian Brown" <jul...@codesourcery.com> wrote: >> * Load/store multiple instructions: GCC only generates these from >> load_multiple/store_multiple (from a couple of places where hard >> registers are already known, e.g. function prologues & epilogues), >> or using peepholes. All ARM chips support much more generality for >> the latter: e.g. sparse sets of registers, and transfers of more >> than four registers. Maybe a pass can be added to somehow take >> better advantage of those. > > > Also keep in mind the constraint of increasing register numbers getting > increasing addresses this pass has to run after reg-allocation or we need to > teach GCC to assign registers according to these constraints.
There was an example that came up on irc the other day of a bit of inline asm that wanted to use ldm/stm and so had to explicitly assign all its inputs/outputs to fixed registers (which in turn meant it didn't work when compiled for thumb because it was using r7 which was the frame pointer). Presumably if gcc could assign registers with that sort of constraint it would make this kind of asm a bit cleaner too... -- PMM _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
