On Sat, Nov 27, 2010 at 12:11 AM, Andrew Stubbs <a...@codesourcery.com> wrote: > Hi All, > > As we discussed on Monday, I think it might be helpful to get a number of > knowledgeable people together on a call to discuss GCC optimization > opportunities. > > So, I'd like to get some idea of who would like to attend, and we'll try to > find a slot we can all make. I'm on vacation next week, so I expect it'll be > in two or three week's time.
To add to the mix: Some ideas that are logged as blueprints: Using ARMv5 saturated instructions (https://blueprints.launchpad.net/gcc-linaro/+spec/armv5-saturated-ops) Using ARMv6 SIMD instructions (https://blueprints.launchpad.net/gcc-linaro/+spec/armv6-simd) Using ARMv7 unaligned accesses (https://blueprints.launchpad.net/gcc-linaro/+spec/unaligned-accesses) Changing the built-in memcpy to use unaligned (https://blueprints.launchpad.net/gcc-linaro/+spec/unaligned-memcpy) The following areas have been suggested. I don't know if they're still valid: Register allocator: The register allocator is designed around the needs of architectures with a low register count and restrictive register classes. The ARM architecture has many general purpose registers. Different assumptions may give better code. Conditional instructions: The ARM and, to a lesser extent, Thumb-2 ISAs allow conditional execution of instructions. This can be used in many situations to eliminate an expensive branch. The middle end expands and transforms branches. The ARM backend tries to recombine the RTL back into conditional instructions, but often can't due to the middle end transforms. -- Michael _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
