gsmiller commented on PR #12417: URL: https://github.com/apache/lucene/pull/12417#issuecomment-1636510014
Now for something possibly more useful. I brought the current vectorized version of ForUtil from this PR over to the local Lucene fork we use for Amazon product search and ran some internal benchmarks (replaying sampled production traffic against a single-box version of our service). I did this on two different AWS ec2 instances, where the baseline uses the ForUtil implementation as it exists on 9.4, and the candidate drops the vectorized implementation in place (along with the slight tweaks to PForUtil, Lucene90PostingsReader and Lucene90PostingsWriter). Note that these benchmarks were running with jdk19 (not 20), so it's possible we'd see something different with 20? First, on an x86-based m4.10xlarge instance [1], the vectorized version appears to provide a ~3% red-line QPS improvement along with a 3.7% avg latency reduction. Next, on an ARM-based (AWS Graviton2) m6g.4xlarge instance[2], I only saw a ~2% red-line QPS improvement and no real avg latency reduction. I'm going to be mostly away from my computer next week, but I may dive into these benchmarks a bit more after that. Thought it could be useful to put these results out there in the meantime though. [1] lscpu info for the m4.10xlarge box: ``` Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 40 On-line CPU(s) list: 0-39 Thread(s) per core: 2 Core(s) per socket: 10 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 63 Model name: Intel(R) Xeon(R) CPU E5-2676 v3 @ 2.40GHz Stepping: 2 CPU MHz: 2700.156 CPU max MHz: 3000.0000 CPU min MHz: 1200.0000 BogoMIPS: 4800.04 Hypervisor vendor: Xen Virtualization type: full L1d cache: 32K L1i cache: 32K L2 cache: 256K L3 cache: 30720K NUMA node0 CPU(s): 0-9,20-29 NUMA node1 CPU(s): 10-19,30-39 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx pdpe1gb rdtscp lm constant_tsc rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq monitor est ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand hypervisor lahf_lm abm cpuid_fault invpcid_single pti fsgsbase bmi1 avx2 smep bmi2 erms invpcid xsaveopt ida ``` [2] lscpu info for the m6g.4xlarge box: ``` Architecture: aarch64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 16 On-line CPU(s) list: 0-15 Thread(s) per core: 1 Core(s) per socket: 16 Socket(s): 1 NUMA node(s): 1 Vendor ID: ARM Model: 1 Model name: Neoverse-N1 Stepping: r3p1 BogoMIPS: 243.75 L1d cache: 64K L1i cache: 64K L2 cache: 1024K L3 cache: 32768K NUMA node0 CPU(s): 0-15 Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs ``` -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: issues-unsubscr...@lucene.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org --------------------------------------------------------------------- To unsubscribe, e-mail: issues-unsubscr...@lucene.apache.org For additional commands, e-mail: issues-h...@lucene.apache.org
