On Thu, Feb 04, 2016 at 06:55:15PM +0200, Jani Nikula wrote: > From: Deepak M <[email protected]> > > Make the gpio read/write functions more generic iosf sideband read/write > functions, taking the iosf port as argument. > > v2: rebase > v3: rebase > v4 by Jani: address Ville's review > v5 by Jani: drop the PCI_DEVFN change (Ville) > > Signed-off-by: Deepak M <[email protected]> > Signed-off-by: Jani Nikula <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +++-- > drivers/gpu/drm/i915/intel_sideband.c | 9 +++++---- > 4 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index bd126ff3a6e2..8216665405eb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -3471,8 +3471,8 @@ int sandybridge_pcode_write(struct drm_i915_private > *dev_priv, u32 mbox, u32 val > u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); > void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); > u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); > -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); > -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); > +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); > +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, > u32 val); > u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); > void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); > u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 6867295dbdc1..6732fc139196 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -618,6 +618,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define IOSF_PORT_CCK 0x14 > #define IOSF_PORT_DPIO_2 0x1a > #define IOSF_PORT_FLISDSI 0x1b > +#define IOSF_PORT_GPIO_SC 0x48 > +#define IOSF_PORT_GPIO_SUS 0xa8 > #define IOSF_PORT_CCU 0xa9 > #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE > + 0x2104) > #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE > + 0x2108) > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > index bcc083db7632..b96ac87902b4 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > @@ -235,14 +235,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi > *intel_dsi, const u8 *data) > if (!gtable[gpio].init) { > /* program the function */ > /* FIXME: remove constant below */ > - vlv_gpio_nc_write(dev_priv, function, 0x2000CC00); > + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function, > + 0x2000CC00); > gtable[gpio].init = 1; > } > > val = 0x4 | action; > > /* pull up/down */ > - vlv_gpio_nc_write(dev_priv, pad, val); > + vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val); > mutex_unlock(&dev_priv->sb_lock); > > out: > diff --git a/drivers/gpu/drm/i915/intel_sideband.c > b/drivers/gpu/drm/i915/intel_sideband.c > index f5b0ab6f5942..c3998188cf35 100644 > --- a/drivers/gpu/drm/i915/intel_sideband.c > +++ b/drivers/gpu/drm/i915/intel_sideband.c > @@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 > addr) > return val; > } > > -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) > +u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg) > { > u32 val = 0; > - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC, > + vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port, > SB_CRRDDA_NP, reg, &val); > return val; > } > > -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) > +void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, > + u8 port, u32 reg, u32 val) > { > - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC, > + vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port, > SB_CRWRDA_NP, reg, &val); > } > > -- > 2.1.4 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
