On Tue, May 05, 2015 at 09:56:02PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2015 at 04:39:21PM +0100, Damien Lespiau wrote:
> > +static void
> > +skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int
> > required_vco)
> > +{
> > + unsigned int min_freq;
> > + u32 val;
> > +
> > + /* select the minimum CDCLK before enabling DPLL 0 */
> > + val = I915_READ(CDCLK_CTL);
> > + val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
> > + val |= CDCLK_FREQ_337_308;
> > +
> > + if (required_vco == 8640)
> > + min_freq = 308570;
> > + else
> > + min_freq = 337500;
> > +
> > + val = CDCLK_FREQ_337_308 | skl_cdlck_decimal(min_freq);
> > +
> > + I915_WRITE(CDCLK_CTL, val);
> > + POSTING_READ(CDCLK_CTL);
> > +
> > + /*
> > + * We always enable DPLL0 with the lowest link rate possible, but still
> > + * taking into account the VCO required to operate the eDP panel at the
> > + * desired frequency. The usual DP link rates operate with a VCO of
> > + * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
> > + * The modeset code is responsible for the selection of the exact link
> > + * rate later on, with the constraint of choosing a frequency that
> > + * works with required_vco.
> > + */
> > + val = I915_READ(DPLL_CTRL1);
> > +
> > + val &= ~(DPLL_CTRL1_HDMI_MODE(0) | DPLL_CTRL1_SSC(0) |
> > + DPLL_CTRL1_LINK_RATE_MASK(0));
> > + val |= DPLL_CTRL1_OVERRIDE(0);
> > + if (required_vco == 8640)
> > + val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
> > + else
> > + val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
>
> Hmm. These new pll registers are very confusing. But looks correct
> based on my understanding.
BTW replacing the magic numbers with some kind of enum for the DPLLs
might make this stuff less confusing.
--
Ville Syrjälä
Intel OTC
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