On Mon, Jun 16, 2014 at 07:51:35PM +0200, Daniel Vetter wrote:
> +void intel_edp_psr_invalidate(struct drm_device *dev,
> + unsigned frontbuffer_bits)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_crtc *crtc;
> + enum pipe pipe;
> +
> + if (!HAS_PSR(dev))
> + return;
if (!psr.enabled)
return;
> +
> +
> + mutex_lock(&dev_priv->psr.lock);
> + crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
> + pipe = to_intel_crtc(crtc)->pipe;
> +
> + intel_edp_psr_do_exit(dev);
> +
> + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> +
> + dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
> + mutex_unlock(&dev_priv->psr.lock);
> +}
> +
> +void intel_edp_psr_flush(struct drm_device *dev,
> + unsigned frontbuffer_bits)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_crtc *crtc;
> + enum pipe pipe;
> +
> + if (!HAS_PSR(dev))
> + return;
if (!psr.enabled)
return;
> +
> +
> + mutex_lock(&dev_priv->psr.lock);
> + crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
> + pipe = to_intel_crtc(crtc)->pipe;
> + dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
> +
> + if (IS_HASWELL(dev) &&
> + (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
> + intel_edp_psr_do_exit(dev);
This deserves comment explaining/referencing the discrepancy.
> + if (!dev_priv->psr.busy_frontbuffer_bits)
> + schedule_delayed_work(&dev_priv->psr.work,
> + msecs_to_jiffies(100));
100ms made sense when queueing the task at the start of the write cycle,
but on flush, it only wants to be ~2frames. As we know we have an active
pipe here we could queue it for exactly N frames...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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